Copyright: Made with the help of Makertf 1.04


About this help file

This file was made with the help of Makertf 1.04 from the input file ../../../gas-980103/gas/doc/as.texinfo.

START-INFO-DIR-ENTRY
* As: (as).                     The GNU assembler.
END-INFO-DIR-ENTRY

This file documents the GNU Assembler "as".

Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.

Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies.

Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one.

Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions.


Using as
Node: Top, Next: Overview, Prev: , Up: (dir)	About this help file

Using as

by Dean Elsner, Jay Fenlason & friends

Using as

This file is a user guide to the GNU assembler as.

* Menu:

Overview	Overview

Invoking	Command-Line Options

Syntax	Syntax

Sections	Sections and Relocation

Symbols	Symbols

Expressions	Expressions

Pseudo Ops	Assembler Directives

Machine Dependencies	Machine Dependent Features

Reporting Bugs	Reporting Bugs

Acknowledgements	Who Did What

Index	Index


Overview
Node: Overview, Next: Invoking, Prev: Top, Up: Top

Overview

Here is a brief summary of how to invoke as.  For details, see Comand-Line Options.

{No Value For "\keep\li720\f1{}AS"} [ -a[cdhlns][=file] ] [ -D ]  [ --defsym sym=val ]
 [ -f ] [ --gstabs ] [ --help ] [ -I dir ] [ -J ] [ -K ] [ -L ]
 [ -o objfile ] [ -R ] [ --statistics ] [ -v ] [ -version ]
 [ --version ] [ -W ] [ -w ] [ -x ] [ -Z ]
 [ -mbig-endian | -mlittle-endian ]
 [ -m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 | -m[arm]6 | -m[arm]7[t][[d]m[i]] ]
 [ -m[arm]v2 | -m[arm]v2a | -m[arm]v3 | -m[arm]v3m | -m[arm]v4 | -m[arm]v4t ]
 [ -mthumb | -mall ]
 [ -mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu ]
 [ -EB | -EL ]
 [ -mapcs-32 | -mapcs-26 ]
 [ -O ]
 [ -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
   -Av8plus | -Av8plusa | -Av9 | -Av9a ]
 [ -xarch=v8plus | -xarch=v8plusa ] [ -bump ] [ -32 | -64 ]
 [ -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC ]
 [ -b ] [ -no-relax ]
 [ -l ] [ -m68000 | -m68010 | -m68020 | ... ]
 [ -nocpp ] [ -EL ] [ -EB ] [ -G num ] [ -mcpu=CPU ]
 [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ]
 [ --trap ] [ --break ]
 [ --emulation=name ]
 [ -- | files ... ]

-a[cdhlmns]

Turn on listings, in any of a variety of ways:

-ac

omit false conditionals

-ad

omit debugging directives

-ah

include high-level source

-al

include assembly

-am

include macro expansions

-an

omit forms processing

-as

include symbols

=file

set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing.  The =file option, if used, must be the last one.  By itself, -a defaults to -ahls.

-D

Ignored.  This option is accepted for script compatibility with calls to other assemblers.

--defsym sym=value

Define the symbol sym to be value before assembling the input file.  value must be an integer constant.  As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value.

-f

"fast"--skip whitespace and comment preprocessing (assume source is compiler output).

--gstabs

Generate stabs debugging information for each assembler line.  This may help debugging assembler code, if the debugger can handle it.

--help

Print a summary of the command line options and exit.

-I dir

Add directory dir to the search list for .include directives.

-J

Don't warn about signed overflow.

-K

Issue warnings when difference tables altered for long displacements.

-L

Keep (in the symbol table) local symbols, starting with L.

-o objfile

Name the object-file output from as objfile.

-R

Fold the data section into the text section.

--statistics

Print the maximum space (in bytes) and total time (in seconds) used by assembly.

-v

-version

Print the as version.

--version

Print the as version and exit.

-W

Suppress warning messages.

-w

Ignored.

-x

Ignored.

-Z

Generate an object file even after errors.

-- | files ...

Standard input, or source files to assemble.

The following options are available when as is configured for an ARC processor.

-mbig-endian

Generate "big endian" format output.

-mlittle-endian

Generate "little endian" format output.

The following options are available when as is configured for the ARM processor family.

-m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 | -m[arm]6 | -m[arm]7[t][[d]m] | -m[arm]v2 | -m[arm]v2a | -m[arm]v3 | -m[arm]v3m | -m[arm]v4 | -m[arm]v4t

Specify which variant of the ARM architecture is the target.

-mthumb | -mall

Enable or disable Thumb only instruction decoding.

-mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu

Select which Floating Point architcture is the target.

-mapcs-32 | -mapcs-26

Select which procedure calling convention is in use.

-EB | -EL

Select either big-endian (-EB) or little-endian (-EL) output.

The following options are available when as is configured for a D10V processor.

-O

Optimize output by parallelizing instructions.

The following options are available when as is configured for the Intel 80960 processor.

-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC

Specify which variant of the 960 architecture is the target.

-b

Add code to collect statistics about branches taken.

-no-relax

Do not alter compare-and-branch instructions for long displacements; error if necessary.

The following options are available when as is configured for the Motorola 68000 series.

-l

Shorten references to undefined symbols, to one word instead of two.

-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060

| -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200

Specify what processor in the 68000 family is the target.  The default is normally the 68020, but this can be changed at configuration time.

-m68881 | -m68882 | -mno-68881 | -mno-68882

The target machine does (or does not) have a floating-point coprocessor.  The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor.

-m68851 | -mno-68851

The target machine does (or does not) have a memory-management unit coprocessor.  The default is to assume an MMU for 68020 and up.

The following options are available when as is configured for the SPARC architecture:

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite

-Av8plus | -Av8plusa | -Av9 | -Av9a

Explicitly select a variant of the SPARC architecture.

-Av8plus and -Av8plusa select a 32 bit environment.  -Av9 and -Av9a select a 64 bit environment.

-Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.

-xarch=v8plus | -xarch=v8plusa

For compatibility with the Solaris v9 assembler.  These options are equivalent to -Av8plus and -Av8plusa, respectively.

-bump

Warn when the assembler switches to another architecture.

The following options are available when as is configured for a MIPS processor.

-G num

This option sets the largest size of an object that can be referenced implicitly with the gp register.  It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix.  The default value is 8.

-EB

Generate "big endian" format output.

-EL

Generate "little endian" format output.

-mips1

-mips2

-mips3

Generate code for a particular MIPS Instruction Set Architecture level.  -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, and -mips3 to the R4000 processor.

-m4650

-no-m4650

Generate code for the MIPS R4650 chip.  This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4650 turns off this option.

-mcpu=CPU

Generate code for a particular MIPS cpu.  This has little effect on the assembler, but it is passed by gcc.

--emulation=name

This option causes as to emulate as configured for some other target, in all respects, including output format (choosing between ELF and ECOFF only), handling of pseudo-opcodes which may generate debugging information or store symbol table information, and default endianness.  The available configuration names are: mipsecoff, mipself, mipslecoff, mipsbecoff, mipslelf, mipsbelf.  The first two do not alter the default endianness from that of the primary target for which the assembler was configured; the others change the default to little- or big-endian as indicated by the b or l in the name.  Using -EB or -EL will override the endianness selection in any case.

This option is currently supported only when the primary target as is configured for is a MIPS ELF or ECOFF target.  Furthermore, the primary target or others specified with --enable-targets=... at configuration time must include support for the other format, if both are to be available.  For example, the Irix 5 configuration includes support for both.

Eventually, this option will support more configurations, with more fine-grained control over the assembler's behavior, and will be supported for more processors.

-nocpp

{No Value For "\li720{}AS"} ignores this option.  It is accepted for compatibility with the native tools.

--trap

--no-trap

--break

--no-break

Control how to deal with multiplication overflow and division by zero.  --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception.

* Menu:

Manual	Structure of this Manual

GNU Assembler	The GNU Assembler

Object Formats	Object File Formats

Command Line	Command Line

Input Files	Input Files

Object	Output (Object) File

Errors	Error and Warning Messages


Structure of this Manual
Node: Manual, Next: GNU Assembler, Prev: , Up: Overview

Structure of this Manual

This manual is intended to describe what you need to know to use GNU as.  We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that as understands; and of course how to invoke as.

This manual also describes some of the machine-dependent features of various flavors of the assembler.

On the other hand, this manual is not intended as an introduction to programming in assembly language--let alone programming in general!  In a similar vein, we make no attempt to introduce the machine architecture; we do not describe the instruction set, standard mnemonics, registers or addressing modes that are standard to a particular architecture.  You may want to consult the manufacturer's machine architecture manual for this information.


The GNU Assembler
Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview

The GNU Assembler

GNU as is really a family of assemblers.  If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture.  Each version has much in common with the others, including object file formats, most assembler directives (often called "pseudo-ops") and assembler syntax.

as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker ld.  Nevertheless, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble.  Any exceptions are documented explicitly (see Machine Dependencies).  This doesn't mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax.

Unlike older assemblers, as is designed to assemble a source program in one pass of the source file.  This has a subtle impact on the .org directive (see .org).


Object File Formats
Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview

Object File Formats

The GNU assembler can be configured to produce several alternative object file formats.  For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different file formats.  See Symbol Attributes.


Command Line
Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview

Command Line

After the program name as, the command line may contain options and file names.  Options may appear in any order, and may be before, after, or between file names.  The order of file names is significant.

-- (two hyphens) by itself names the standard input file explicitly, as one of the files for as to assemble.

Except for -- any command line argument that begins with a hyphen (-) is an option.  Each option changes the behavior of as.  No option changes the way another option works.  An option is a - followed by one or more letters; the case of the letter is important.   All options are optional.

Some options expect exactly one file name to follow them.  The file name may either immediately follow the option's letter (compatible with older assemblers) or it may be the next command argument (GNU standard).  These two command lines are equivalent:

{No Value For "\keep\li720\f1{}AS"} -o my-object-file.o mumble.s
as -omy-object-file.o mumble.s


Input Files
Node: Input Files, Next: Object, Prev: Command Line, Up: Overview

Input Files

We use the phrase "source program", abbreviated "source", to describe the program input to one run of as.  The program may be in one or more files; how the source is partitioned into files doesn't change the meaning of the source.

The source program is a concatenation of the text in all the files, in the order specified.

Each time you run as it assembles exactly one source program.  The source program is made up of one or more files.  (The standard input is also a file.)

You give as a command line that has zero or more input file names.  The input files are read (from left file name to right).  A command line argument (in any position) that has no special meaning is taken to be an input file name.

If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal.  You may have to type ctl-D to tell as there is no more program to assemble.

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file.

Filenames and Line-numbers

There are two ways of locating a line in the input file (or files) and either may be used in reporting error messages.  One way refers to a line number in a physical file; the other refers to a line number in a "logical" file.  See Error and Warning Messages.

"Physical files" are those files named in the command line given to as.

"Logical files" are simply names declared explicitly by assembler directives; they bear no relation to physical files.  Logical file names help error messages reflect the original source file, when as source is itself synthesized from other files.  See .app-file.


Output (Object) File
Node: Object, Next: Errors, Prev: Input Files, Up: Overview

Output (Object) File

Every time you run as it produces an output file, which is your assembly language program translated into numbers.  This file is the object file.  Its default name is a.out, or b.out when as is configured for the Intel 80960.  You can give it another name by using the -o option.  Conventionally, object file names end with .o.  The default name is used for historical reasons: older assemblers were capable of assembling self-contained programs directly into a runnable program.  (For some formats, this isn't currently possible, but it can be done for the a.out format.)

The object file is meant for input to the linker ld.  It contains assembled program code, information to help ld integrate the assembled program into a runnable file, and (optionally) symbolic information for the debugger.


Error and Warning Messages
Node: Errors, Next: , Prev: Object, Up: Overview

Error and Warning Messages

as may write warnings and error messages to the standard error file (usually your terminal).  This should not happen when  a compiler runs as automatically.  Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.

Warning messages have the format

file_name:NNN:Warning Message Text

(where NNN is a line number).  If a logical file name has been given (see .app-file) it is used for the filename, otherwise the name of the current input file is used.  If a logical line number was given (see .line) then it is used to calculate the number printed, otherwise the actual line in the current source file is printed.  The message text is intended to be self explanatory (in the grand Unix tradition).

Error messages have the format

file_name:NNN:FATAL:Error Message Text

The file name and line number are derived as for warning messages.  The actual message text may be rather less explanatory because many of them aren't supposed to happen.


Command-Line Options
Node: Invoking, Next: Syntax, Prev: Overview, Up: Top

Command-Line Options

This chapter describes command-line options available in all versions of the GNU assembler; see Machine Dependencies, for options specific to particular machine architectures.

If you are invoking as via the GNU C compiler (version 2), you can use the -Wa option to pass arguments through to the assembler.  The assembler arguments must be separated from each other (and the -Wa) by commas.  For example:

gcc -c -g -O -Wa,-alh,-L file.c

emits a listing to standard output with high-level and assembly source.

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler.  (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.)

* Menu:

a	-a[cdhlns] enable listings

D	-D for compatibility

f	-f to work faster

I	-I for .include search path

K	-K for difference tables

L	-L to retain local labels

M	-M or -mri to assemble in MRI compatibility mode

MD	-MD for dependency tracking

o	-o to name the object file

R	-R to join data and text sections

statistics	-statistics to see statistics about assembly

v	-v to announce version

W	-W to suppress warnings

Z	-Z to make object file even after errors


Enable Listings: -a[cdhlns]
Node: a, Next: D, Prev: , Up: Invoking

Enable Listings: -a[cdhlns]

These options enable listing output from the assembler.  By itself, -a requests high-level, assembly, and symbols listing.  You can use other letters to select specific options for the list: -ah requests a high-level language listing, -al requests an output-program assembly listing, and -as requests a symbol table listing.  High-level listings require that a compiler debugging option like -g be used, and that assembly listings (-al) be requested also.

Use the -ac option to omit false conditionals from a listing.  Any lines which are not assembled because of a false .if (or .ifdef, or any other conditional), or a true .if followed by an .else, will be omitted from the listing.

Use the -ad option to omit debugging directives from the listing.

Once you have specified one of these options, you can further control listing output and its appearance using the directives .list, .nolist, .psize, .eject, .title, and .sbttl.  The -an option turns off all forms processing.  If you do not request listing output with one of the -a options, the listing-control directives have no effect.

The letters after -a may be combined into one option, e.g., -aln.


-D
Node: D, Next: f, Prev: a, Up: Invoking

-D

This option has no effect whatsoever, but it is accepted to make it more likely that scripts written for other assemblers also work with as.


Work Faster: -f
Node: f, Next: I, Prev: D, Up: Invoking

Work Faster: -f

-f should only be used when assembling programs written by a (trusted) compiler.  -f stops the assembler from doing whitespace and comment preprocessing on the input file(s) before assembling them.  See Preprocessing.

Warning: if you use -f when the files actually need to be preprocessed (if they contain comments, for example), as does not work correctly.


.includesearch path: -Ipath
Node: I, Next: K, Prev: f, Up: Invoking

.include search path: -I path

Use this option to add a path to the list of directories as searches for files specified in .include directives (see .include).  You may use -I as many times as necessary to include a variety of paths.  The current working directory is always searched first; after that, as searches any -I directories in the same order as they were specified (left to right) on the command line.


Difference Tables: -K
Node: K, Next: L, Prev: I, Up: Invoking

Difference Tables: -K

as sometimes alters the code emitted for directives of the form .word sym1-sym2; see .word.  You can use the -K option if you want a warning issued when this is done.


Include Local Labels: -L
Node: L, Next: M, Prev: K, Up: Invoking

Include Local Labels: -L

Labels beginning with L (upper case only) are called "local labels". See Symbol Names.  Normally you do not see such labels when debugging, because they are intended for the use of programs (like compilers) that compose assembler programs, not for your notice.  Normally both as and ld discard such labels, so you do not normally debug with them.

This option tells as to retain those L... symbols in the object file.  Usually if you do this you also tell the linker ld to preserve symbols whose names begin with L.

By default, a local label is any label beginning with L, but each target is allowed to redefine the local label prefix.  On the HPPA local labels begin with L$.  ; for the ARM family;


Assemble in MRI Compatibility Mode: -M
Node: M, Next: MD, Prev: L, Up: Invoking

Assemble in MRI Compatibility Mode: -M

The -M or --mri option selects MRI compatibility mode.  This changes the syntax and pseudo-op handling of as to make it compatible with the ASM68K or the ASM960 (depending upon the configured target) assembler from Microtec Research.  The exact nature of the MRI syntax will not be documented here; see the MRI manuals for more information.  Note in particular that the handling of macros and macro arguments is somewhat different.  The purpose of this option is to permit assembling existing MRI assembler code using as.

The MRI compatibility is not complete.  Certain operations of the MRI assembler depend upon its object file format, and can not be supported using other object file formats.  Supporting these would require enhancing each object file format individually.  These are:

•	global symbols in common section

The m68k MRI assembler supports common sections which are merged by the linker.  Other object file formats do not support this.  as handles common sections by treating them as a single common symbol.  It permits local symbols to be defined within a common section, but it can not support global symbols, since it has no way to describe them.

•	complex relocations

The MRI assemblers support relocations against a negated section address, and relocations which combine the start addresses of two or more sections.  These are not support by other object file formats.

•	END pseudo-op specifying start address

The MRI END pseudo-op permits the specification of a start address.  This is not supported by other object file formats.  The start address may instead be specified using the -e option to the linker, or in a linker script.

•	IDNT, .ident and NAME pseudo-ops

The MRI IDNT, .ident and NAME pseudo-ops assign a module name to the output file.  This is not supported by other object file formats.

•	ORG pseudo-op

The m68k MRI ORG pseudo-op begins an absolute section at a given address.  This differs from the usual as .org pseudo-op, which changes the location within the current section.  Absolute sections are not supported by other object file formats.  The address of a section may be assigned within a linker script.

There are some other features of the MRI assembler which are not supported by as, typically either because they are difficult or because they seem of little consequence.  Some of these may be supported in future releases.

•	EBCDIC strings

EBCDIC strings are not supported.

•	packed binary coded decimal

Packed binary coded decimal is not supported.  This means that the DC.P and DCB.P pseudo-ops are not supported.

•	FEQU pseudo-op

The m68k FEQU pseudo-op is not supported.

•	NOOBJ pseudo-op

The m68k NOOBJ pseudo-op is not supported.

•	OPT branch control options

The m68k OPT branch control options--B, BRS, BRB, BRL, and BRW--are ignored.  as automatically relaxes all branches, whether forward or backward, to an appropriate size, so these options serve no purpose.

•	OPT list control options

The following m68k OPT list control options are ignored: C, CEX, CL, CRE, E, G, I, M, MEX, MC, MD, X.

•	other OPT options

The following m68k OPT options are ignored: NEST, O, OLD, OP, P, PCO, PCR, PCS, R.

•	OPT D option is default

The m68k OPT D option is the default, unlike the MRI assembler.  OPT NOD may be used to turn it off.

•	XREF pseudo-op.

The m68k XREF pseudo-op is ignored.

•	.debug pseudo-op

The i960 .debug pseudo-op is not supported.

•	.extended pseudo-op

The i960 .extended pseudo-op is not supported.

•	.list pseudo-op.

The various options of the i960 .list pseudo-op are not supported.

•	.optimize pseudo-op

The i960 .optimize pseudo-op is not supported.

•	.output pseudo-op

The i960 .output pseudo-op is not supported.

•	.setreal pseudo-op

The i960 .setreal pseudo-op is not supported.


Dependency tracking: --MD
Node: MD, Next: o, Prev: M, Up: Invoking

Dependency tracking: --MD

as can generate a dependency file for the file it creates.  This file consists of a single rule suitable for make describing the dependencies of the main source file.

The rule is written to the file named in its argument.

This feature is used in the automatic updating of makefiles.


Name the Object File: -o
Node: o, Next: R, Prev: MD, Up: Invoking

Name the Object File: -o

There is always one object file output when you run as.  By default it has the name a.out (or b.out, for Intel 960 targets only).  You use this option (which takes exactly one filename) to give the object file a different name.

Whatever the object file is called, as overwrites any existing file of the same name.


Join Data and Text Sections: -R
Node: R, Next: statistics, Prev: o, Up: Invoking

Join Data and Text Sections: -R

-R tells as to write the object file as if all data-section data lives in the text section.  This is only done at the very last moment:  your binary data are the same, but data section parts are relocated differently.  The data section part of your object file is zero bytes long because all its bytes are appended to the text section.  (See Sections and Relocation.)

When you specify -R it would be possible to generate shorter address displacements (because we do not have to cross between text and data section).  We refrain from doing this simply for compatibility with older versions of as.  In future, -R may work this way.

When as is configured for COFF output, this option is only useful if you use sections named .text and .data.

-R is not supported for any of the HPPA targets.  Using -R generates a warning from as.


Display Assembly Statistics: --statistics
Node: statistics, Next: v, Prev: R, Up: Invoking

Display Assembly Statistics: --statistics

Use --statistics to display two statistics about the resources used by as: the maximum amount of space allocated during the assembly (in bytes), and the total execution time taken for the assembly (in CPU seconds).


Announce Version: -v
Node: v, Next: W, Prev: statistics, Up: Invoking

Announce Version: -v

You can find out what version of as is running by including the option -v (which you can also spell as -version) on the command line.


Suppress Warnings: -W
Node: W, Next: Z, Prev: v, Up: Invoking

Suppress Warnings: -W

as should never give a warning or error message when assembling compiler output.  But programs written by people often cause as to give a warning that a particular assumption was made.  All such warnings are directed to the standard error file.  If you use this option, no warnings are issued.  This option only affects the warning messages: it does not change any particular of how as assembles your file.  Errors, which stop the assembly, are still reported.


Generate Object File in Spite of Errors: -Z
Node: Z, Next: , Prev: W, Up: Invoking

Generate Object File in Spite of Errors: -Z

After an error message, as normally produces no output.  If for some reason you are interested in object file output even after as gives an error message on your program, use the -Z option.  If there are any errors, as continues anyways, and writes an object file after a final warning message of the form n errors, m warnings, generating bad object file.


Syntax
Node: Syntax, Next: Sections, Prev: Invoking, Up: Top

Syntax

This chapter describes the machine-independent syntax allowed in a source file.  as syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except that as does not assemble Vax bit-fields.

* Menu:

Preprocessing	Preprocessing

Whitespace	Whitespace

Comments	Comments

Symbol Intro	Symbols

Statements	Statements

Constants	Constants


Preprocessing
Node: Preprocessing, Next: Whitespace, Prev: , Up: Syntax

Preprocessing

The as internal preprocessor:

•	adjusts and removes extra whitespace.  It leaves one space or tab before the keywords on a line, and turns any other whitespace on the line into a single space.

•	removes all comments, replacing them with a single space, or an appropriate number of newlines.

•	converts character constants into the appropriate numeric values.

It does not do macro processing, include file handling, or anything else you may get from your C compiler's preprocessor.  You can do include file processing with the .include directive (see .include).  You can use the GNU C compiler driver to get other "CPP" style preprocessing, by giving the input file a .S suffix.  See Options Controlling the Kind of Output.

Excess whitespace, comments, and character constants cannot be used in the portions of the input text that are not preprocessed.

If the first line of an input file is #NO_APP or if you use the -f option, whitespace and comments are not removed from the input file.  Within an input file, you can ask for whitespace and comment removal in specific portions of the by putting a line that says #APP before the text that may contain whitespace or comments, and putting a line that says #NO_APP after this text.  This feature is mainly intend to support asm statements in compilers whose output is otherwise free of comments and whitespace.


Whitespace
Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax

Whitespace

"Whitespace" is one or more blanks or tabs, in any order.  Whitespace is used to separate symbols, and to make programs neater for people to read.  Unless within character constants (see Character Constants), any whitespace means the same as exactly one space.


Comments
Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax

Comments

There are two ways of rendering comments to as.  In both cases the comment is equivalent to one space.

Anything from /* through the next */ is a comment.  This means you may not nest these comments.

/*
  The only way to include a newline ('\n') in a comment
  is to use this sort of comment.
*/

/* This sort of comment does not nest. */

Anything from the "line comment" character to the next newline is considered a comment and is ignored.  The line comment character is ; for the AMD 29K family; ; on the ARC; ; for the H8/300 family; ! for the H8/500 family; ; for the HPPA; # on the i960; ! for the Hitachi SH; ! on the SPARC; # on the m32r; | on the 680x0; # on the Vax; ! for the Z8000; # on the V850; see Machine Dependencies.

On some machines there are two different line comment characters.  One character only begins a comment if it is the first non-whitespace character on a line, while the other always begins a comment.

The V850 assembler also supports a double dash as starting a comment that extends to the end of the line.

--;

To be compatible with past assemblers, lines that begin with # have a special interpretation.  Following the # should be an absolute expression (see Expressions): the logical line number of the next line.  Then a string (see Strings) is allowed: if present it is a new logical file name.  The rest of the line, if any, should be whitespace.

If the first non-whitespace characters on the line are not numeric, the line is ignored.  (Just like a comment.)

                          # This is an ordinary comment.
# 42-6 "new_file_name"    # New logical file name
                          # This is logical line # 36.

This feature is deprecated, and may disappear from future versions of as.


Symbols
Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax

Symbols

A "symbol" is one or more characters chosen from the set of all letters (both upper and lower case), digits and the three characters _.$.  On most machines, you can also use $ in symbol names; exceptions are noted in Machine Dependencies.  No symbol may begin with a digit.  Case is significant.  There is no length limit: all characters are significant.  Symbols are delimited by characters not in that set, or by the beginning of a file (since the source program must end with a newline, the end of a file is not a possible symbol delimiter).  See Symbols.


Statements
Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax

Statements

A "statement" ends at a newline character (\n) or line separator character.  (The line separator is usually ;, unless this conflicts with the comment character; see Machine Dependencies.)  The newline or separator character is considered part of the preceding statement.  Newlines and separators within character constants are an exception: they do not end statements.

It is an error to end any statement with end-of-file:  the last character of any input file should be a newline.

You may write a statement on more than one line if you put a backslash (\) immediately in front of any newlines within the statement.  When as reads a backslashed newline both characters are ignored.  You can even put backslashed newlines in the middle of symbol names without changing the meaning of your source program.

An empty statement is allowed, and may include whitespace.  It is ignored.

A statement begins with zero or more labels, optionally followed by a key symbol which determines what kind of statement it is.  The key symbol determines the syntax of the rest of the statement.  If the symbol begins with a dot . then the statement is an assembler directive: typically valid for any computer.  If the symbol begins with a letter the statement is an assembly language "instruction": it assembles into a machine language instruction.  Different versions of as for different computers recognize different instructions.  In fact, the same symbol may represent a different instruction in a different computer's assembly language.

A label is a symbol immediately followed by a colon (:).  Whitespace before a label or after a colon is permitted, but you may not have whitespace between a label's symbol and its colon. See Labels.

For HPPA targets, labels need not be immediately followed by a colon, but the definition of a label must begin in column zero.  This also implies that only one label may be defined on each line.

label:     .directive    followed by something
another_label:           # This is an empty statement.
           instruction   operand_1, operand_2, ...


Constants
Node: Constants, Next: , Prev: Statements, Up: Syntax

Constants

A constant is a number, written so that its value is known by inspection, without knowing any context.  Like this:

.byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
.ascii "Ring the bell\7"                  # A string constant.
.octa  0x123456789abcdef0123456789ABCDEF0 # A bignum.
.float 0f-314159265358979323846264338327\
95028841971.693993751E-40                 # - pi, a flonum.

* Menu:

Characters	Character Constants

Numbers	Number Constants


Character Constants
Node: Characters, Next: Numbers, Prev: , Up: Constants

Character Constants

There are two kinds of character constants.  A "character" stands for one character in one byte and its value may be used in numeric expressions.  String constants (properly called string literals) are potentially many bytes and their values may not be used in arithmetic expressions.

* Menu:

Strings	Strings

Chars	Characters


Strings
Node: Strings, Next: Chars, Prev: , Up: Characters

Strings

A "string" is written between double-quotes.  It may contain double-quotes or null characters.  The way to get special characters into a string is to "escape" these characters: precede them with a backslash \ character.  For example \\ represents one backslash:  the first \ is an escape which tells as to interpret the second character literally as a backslash (which prevents as from recognizing the second \ as an escape character).  The complete list of escapes follows.

\b

Mnemonic for backspace; for ASCII this is octal code 010.

\f

Mnemonic for FormFeed; for ASCII this is octal code 014.

\n

Mnemonic for newline; for ASCII this is octal code 012.

\r

Mnemonic for carriage-Return; for ASCII this is octal code 015.

\t

Mnemonic for horizontal Tab; for ASCII this is octal code 011.

\ digit digit digit

An octal character code.  The numeric code is 3 octal digits.  For compatibility with other Unix systems, 8 and 9 are accepted as digits: for example, \008 has the value 010, and \009 the value 011.

\x hex-digits...

A hex character code.  All trailing hex digits are combined.  Either upper or lower case x works.

\\

Represents one \ character.

\"

Represents one " character.  Needed in strings to represent this character, because an unescaped " would end the string.

\ anything-else

Any other character when escaped by \ gives a warning, but assembles as if the \ was not present.  The idea is that if you used an escape sequence you clearly didn't want the literal interpretation of the following character.  However as has no other interpretation, so as knows it is giving you the wrong code and warns you of the fact.

Which characters are escapable, and what those escapes represent, varies widely among assemblers.  The current set is what we think the BSD 4.2 assembler recognizes, and is a subset of what most C compilers recognize.  If you are in doubt, do not use an escape sequence.


Characters
Node: Chars, Next: , Prev: Strings, Up: Characters

Characters

A single character may be written as a single quote immediately followed by that character.  The same escapes apply to characters as to strings.  So if you want to write the character backslash, you must write '\\ where the first \ escapes the second \.  As you can see, the quote is an acute accent, not a grave accent.  A newline immediately following an acute accent is taken as a literal character and does not count as the end of a statement.  The value of a character constant in a numeric expression is the machine's byte-wide code for that character.  as assumes your character code is ASCII: 'A means 65, 'B means 66, and so on.


Number Constants
Node: Numbers, Next: , Prev: Characters, Up: Constants

Number Constants

as distinguishes three kinds of numbers according to how they are stored in the target machine.  Integers are numbers that would fit into an int in the C language.  Bignums are integers, but they are stored in more than 32 bits.  Flonums are floating point numbers, described below.

* Menu:

Integers	Integers

Bignums	Bignums

Flonums	Flonums


Integers
Node: Integers, Next: Bignums, Prev: , Up: Numbers

Integers

A binary integer is 0b or 0B followed by zero or more of the binary digits 01.

An octal integer is 0 followed by zero or more of the octal digits (01234567).

A decimal integer starts with a non-zero digit followed by zero or more digits (0123456789).

A hexadecimal integer is 0x or 0X followed by one or more hexadecimal digits chosen from 0123456789abcdefABCDEF.

Integers have the usual values.  To denote a negative integer, use the prefix operator - discussed under expressions (see Prefix Operators).


Bignums
Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers

Bignums

A "bignum" has the same syntax and semantics as an integer except that the number (or its negative) takes more than 32 bits to represent in binary.  The distinction is made because in some places integers are permitted while bignums are not.


Flonums
Node: Flonums, Next: , Prev: Bignums, Up: Numbers

Flonums

A "flonum" represents a floating point number.  The translation is indirect: a decimal floating point number from the text is converted by as to a generic binary floating point number of more than sufficient precision.  This generic floating point number is converted to a particular computer's floating point format (or formats) by a portion of as specialized to that computer.

A flonum is written by writing (in order)

•	The digit 0.  (0 is optional on the HPPA.)

•	A letter, to tell as the rest of the number is a flonum.  e is recommended.  Case is not important.

On the H8/300, H8/500, Hitachi SH, and AMD 29K architectures, the letter must be one of the letters DFPRSX (in upper or lower case).

On the ARC, the letter must be one of the letters DFRS (in upper or lower case).

On the Intel 960 architecture, the letter must be one of the letters DFT (in upper or lower case).

On the HPPA architecture, the letter must be E (upper case only).

•	An optional sign: either + or -.

•	An optional "integer part": zero or more decimal digits.

•	An optional "fractional part": . followed by zero or more decimal digits.

•	An optional exponent, consisting of:

•	An E or e.

•	Optional sign: either + or -.

•	One or more decimal digits.

At least one of the integer part or the fractional part must be present.  The floating point number has the usual base-10 value.

{No Value For "rd{}AS"} does all processing using integers.  Flonums are computed independently of any floating point hardware in the computer running as.


Sections and Relocation
Node: Sections, Next: Symbols, Prev: Syntax, Up: Top

Sections and Relocation

* Menu:

Secs Background	Background

Ld Sections	Linker Sections

As Sections	Assembler Internal Sections

Sub-Sections	Sub-Sections

bss	bss Section


Background
Node: Secs Background, Next: Ld Sections, Prev: , Up: Sections

Background

Roughly, a section is a range of addresses, with no gaps; all data "in" those addresses is treated the same for some particular purpose.  For example there may be a "read only" section.

The linker ld reads many object files (partial programs) and combines their contents to form a runnable program.  When as emits an object file, the partial program is assumed to start at address 0.  ld assigns the final addresses for the partial program, so that different partial programs do not overlap.  This is actually an oversimplification, but it suffices to explain how as uses sections.

{No Value For "rd{}LD"} moves blocks of bytes of your program to their run-time addresses.  These blocks slide to their run-time addresses as rigid units; their length does not change and neither does the order of bytes within them.  Such a rigid unit is called a section.  Assigning run-time addresses to sections is called "relocation".  It includes the task of adjusting mentions of object-file addresses so they refer to the proper run-time addresses.  For the H8/300 and H8/500, and for the Hitachi SH, as pads sections if needed to ensure they end on a word (sixteen bit) boundary.

An object file written by as has at least three sections, any of which may be empty.  These are named "text", "data" and "bss" sections.

When it generates COFF output, as can also generate whatever other named sections you specify using the .section directive (see .section).  If you do not use any directives that place output in the .text or .data sections, these sections still exist, but are empty.

When as generates SOM or ELF output for the HPPA, as can also generate whatever other named sections you specify using the .space and .subspace directives.  See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for details on the .space and .subspace assembler directives.

Additionally, as uses different names for the standard text, data, and bss sections when generating SOM output.  Program text is placed into the $CODE$ section, data into $DATA$, and BSS into $BSS$.

Within the object file, the text section starts at address 0, the data section follows, and the bss section follows the data section.

When generating either SOM or ELF output files on the HPPA, the text section starts at address 0, the data section at address 0x4000000, and the bss section follows the data section.

To let ld know which data changes when the sections are relocated, and how to change that data, as also writes to the object file details of the relocation needed.  To perform relocation ld must know, each time an address in the object file is mentioned:

•	Where in the object file is the beginning of this reference to an address?

•	How long (in bytes) is this reference?

•	Which section does the address refer to?  What is the numeric value of

(address) - (start-address of section)?

•	Is the reference to an address "Program-Counter relative"?

In fact, every address as ever uses is expressed as

(section) + (offset into section)

Further, most expressions as computes have this section-relative nature.  (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.)

In this manual we use the notation {secname N} to mean "offset N into section secname."

Apart from text, data and bss sections you need to know about the "absolute" section.  When ld mixes partial programs, addresses in the absolute section remain unchanged.  For example, address {absolute 0} is "relocated" to run-time address 0 by ld.  Although the linker never arranges two partial programs' data sections with overlapping addresses after linking, by definition their absolute sections must overlap.  Address {absolute 239} in one part of a program is always the same address when the program is running as address {absolute 239} in any other part of the program.

The idea of sections is extended to the "undefined" section.  Any address whose section is unknown at assembly time is by definition rendered {undefined U}--where U is filled in later.  Since numbers are always defined, the only way to generate an undefined address is to mention an undefined symbol.  A reference to a named common block would be such a symbol: its value is unknown at assembly time so it has section undefined.

By analogy the word section is used to describe groups of sections in the linked program.  ld puts all partial programs' text sections in contiguous addresses in the linked program.  It is customary to refer to the text section of a program, meaning all the addresses of all partial programs' text sections.  Likewise for data and bss sections.

Some sections are manipulated by ld; others are invented for use of as and have no meaning except during assembly.


Linker Sections
Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections

Linker Sections

{No Value For "rd{}LD"} deals with just four kinds of sections, summarized below.

named sections

text section

data section

These sections hold your program.  as and ld treat them as separate but equal sections.  Anything you can say of one section is true another.  When the program is running, however, it is customary for the text section to be unalterable.  The text section is often shared among processes: it contains instructions, constants and the like.  The data section of a running program is usually alterable: for example, C variables would be stored in the data section.

bss section

This section contains zeroed bytes when your program begins running.  It is used to hold unitialized variables or common storage.  The length of each partial program's bss section is important, but because it starts out containing zeroed bytes there is no need to store explicit zero bytes in the object file.  The bss section was invented to eliminate those explicit zeros from object files.

absolute section

Address 0 of this section is always "relocated" to runtime address 0.  This is useful if you want to refer to an address that ld must not change when relocating.  In this sense we speak of absolute addresses being "unrelocatable": they do not change during relocation.

undefined section

This "section" is a catch-all for address references to objects not in the preceding sections.

An idealized example of three relocatable sections follows.  The example uses the traditional section names .text and .data.  Memory addresses are on the horizontal axis.

                      +-----+----+--+
partial program # 1:  |ttttt|dddd|00|
                      +-----+----+--+

                      text   data bss
                      seg.   seg. seg.

                      +---+---+---+
partial program # 2:  |TTT|DDD|000|
                      +---+---+---+

                      +--+---+-----+--+----+---+-----+~~
linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
                      +--+---+-----+--+----+---+-----+~~

    addresses:        0 ...


Assembler Internal Sections
Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections

Assembler Internal Sections

These sections are meant only for the internal use of as.  They have no meaning at run-time.  You do not really need to know about these sections for most purposes; but they can be mentioned in as warning messages, so it might be helpful to have an idea of their meanings to as.  These sections are used to permit the value of every expression in your assembly language program to be a section-relative address.

ASSEMBLER-INTERNAL-LOGIC-ERROR!

An internal assembler logic error has been found.  This means there is a bug in the assembler.

expr section

The assembler stores complex expression internally as combinations of symbols.  When it needs to represent an expression as a symbol, it puts it in the expr section.


Sub-Sections
Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections

Sub-Sections

Assembled bytes conventionally fall into two sections: text and data.  You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not contiguous in the assembler source.  as allows you to use "subsections" for this purpose.  Within each section, there can be numbered subsections with values from 0 to 8192.  Objects assembled into the same subsection go into the object file together with other objects in the same subsection.  For example, a compiler might want to store constants in the text section, but might not want to have them interspersed with the program being assembled.  In this case, the compiler could issue a .text 0 before each section of code being output, and a .text 1 before each group of constants being output.

Subsections are optional.  If you do not use subsections, everything goes in subsection number zero.

Each subsection is zero-padded up to a multiple of four bytes.  (Subsections may be padded a different amount on different flavors of as.)

Subsections appear in your object file in numeric order, lowest numbered to highest.  (All this to be compatible with other people's assemblers.) The object file contains no representation of subsections; ld and other programs that manipulate object files see no trace of them.  They just see all your text subsections as a text section, and all your data subsections as a data section.

To specify which subsection you want subsequent statements assembled into, use a numeric argument to specify it, in a .text expression or a .data expression statement.  When generating COFF output, you can also use an extra subsection argument with arbitrary named sections: .section name, expression.  Expression should be an absolute expression.  (See Expressions.)  If you just say .text then .text 0 is assumed.  Likewise .data means .data 0.  Assembly begins in text 0.  For instance:

.text 0     # The default subsection is text 0 anyway.
.ascii "This lives in the first text subsection. *"
.text 1
.ascii "But this lives in the second text subsection."
.data 0
.ascii "This lives in the data section,"
.ascii "in the first data subsection."
.text 0
.ascii "This lives in the first text section,"
.ascii "immediately following the asterisk (*)."

Each section has a "location counter" incremented by one for every byte assembled into that section.  Because subsections are merely a convenience restricted to as there is no concept of a subsection location counter.  There is no way to directly manipulate a location counter--but the .align directive changes it, and any label definition captures its current value.  The location counter of the section where statements are being assembled is said to be the "active" location counter.


bss Section
Node: bss, Next: , Prev: Sub-Sections, Up: Sections

bss Section

The bss section is used for local common variable storage.  You may allocate address space in the bss section, but you may not dictate data to load into it before your program executes.  When your program starts running, all the contents of the bss section are zeroed bytes.

The .lcomm pseudo-op defines a symbol in the bss section; see .lcomm.

The .comm pseudo-op may be used to declare a common symbol, which is another form of uninitialized symbol; see See .comm.

When assembling for a target which supports multiple sections, such as ELF or COFF, you may switch into the .bss section and define symbols as usual; see .section.  You may only assemble zero values into the section.  Typically the section will only contain symbol definitions and .skip directives (see .skip).


Symbols
Node: Symbols, Next: Expressions, Prev: Sections, Up: Top

Symbols

Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug.

Warning: as does not place symbols in the object file in the same order they were declared.  This may break some debuggers.

* Menu:

Labels	Labels

Setting Symbols	Giving Symbols Other Values

Symbol Names	Symbol Names

Dot	The Special Dot Symbol

Symbol Attributes	Symbol Attributes


Labels
Node: Labels, Next: Setting Symbols, Prev: , Up: Symbols

Labels

A "label" is written as a symbol immediately followed by a colon :.  The symbol then represents the current value of the active location counter, and is, for example, a suitable instruction operand.  You are warned if you use the same symbol to represent two different locations: the first definition overrides any other definitions.

On the HPPA, the usual form for a label need not be immediately followed by a colon, but instead must start in column zero.  Only one label may be defined on a single line.  To work around this, the HPPA version of as also provides a special directive .label for defining labels more flexibly.


Giving Symbols Other Values
Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols

Giving Symbols Other Values

A symbol can be given an arbitrary value by writing a symbol, followed by an equals sign =, followed by an expression (see Expressions).  This is equivalent to using the .set directive.  See .set.


Symbol Names
Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols

Symbol Names

Symbol names begin with a letter or with one of ._.  On most machines, you can also use $ in symbol names; exceptions are noted in Machine Dependencies.  That character may be followed by any string of digits, letters, dollar signs (unless otherwise noted in Machine Dependencies), and underscores.  For the AMD 29K family, ? is also allowed in the body of a symbol name, though not at its beginning.

Case of letters is significant: foo is a different symbol name than Foo.

Each symbol has exactly one name.  Each name in an assembly language program refers to exactly one symbol.  You may use that symbol name any number of times in a program.

Local Symbol Names

Local symbols help compilers and programmers use names temporarily.  There are ten local symbol names, which are re-used throughout the program.  You may refer to them using the names 0 1 ... 9.  To define a local symbol, write a label of the form N: (where N represents any digit).  To refer to the most recent previous definition of that symbol write Nb, using the same digit as when you defined the label.  To refer to the next definition of a local label, write Nf--where N gives you a choice of 10 forward references.  The b stands for "backwards" and the f stands for "forwards".

Local symbols are not emitted by the current GNU C compiler.

There is no restriction on how you can use these labels, but remember that at any point in the assembly you can refer to at most 10 prior local labels and to at most 10 forward local labels.

Local symbol names are only a notation device.  They are immediately transformed into more conventional symbol names before the assembler uses them.  The symbol names stored in the symbol table, appearing in error messages and optionally emitted to the object file have these parts:

L

All local labels begin with L. Normally both as and ld forget symbols that start with L. These labels are used for symbols you are never intended to see.  If you use the -L option then as retains these symbols in the object file. If you also instruct ld to retain these symbols, you may use them in debugging.

digit

If the label is written 0: then the digit is 0.  If the label is written 1: then the digit is 1.  And so on up through 9:.

C-A

This unusual character is included so you do not accidentally invent a symbol of the same name.  The character has ASCII value \001.

ordinal number

This is a serial number to keep the labels distinct.  The first 0: gets the number 1; The 15th 0: gets the number 15; etc..  Likewise for the other labels 1: through 9:.

For instance, the first 1: is named L1C-A1, the 44th 3: is named L3C-A44.


The Special Dot Symbol
Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols

The Special Dot Symbol

The special symbol . refers to the current address that as is assembling into.  Thus, the expression melvin: .long . defines melvin to contain its own address.  Assigning a value to . is treated the same as a .org directive.  Thus, the expression .=.+4 is the same as saying .space 4.


Symbol Attributes
Node: Symbol Attributes, Next: , Prev: Dot, Up: Symbols

Symbol Attributes

Every symbol has, as well as its name, the attributes "Value" and "Type".  Depending on output format, symbols can also have auxiliary attributes.

If you use a symbol without defining it, as assumes zero for all these attributes, and probably won't warn you.  This makes the symbol an externally defined symbol, which is generally what you would want.

* Menu:

Symbol Value	Value

Symbol Type	Type

a.out Symbols	Symbol Attributes: a.out

COFF Symbols	Symbol Attributes for COFF

SOM Symbols	Symbol Attributes for SOM


Value
Node: Symbol Value, Next: Symbol Type, Prev: , Up: Symbol Attributes

Value

The value of a symbol is (usually) 32 bits.  For a symbol which labels a location in the text, data, bss or absolute sections the value is the number of addresses from the start of that section to the label.  Naturally for text, data and bss sections the value of a symbol changes as ld changes section base addresses during linking.  Absolute symbols' values do not change during linking: that is why they are called absolute.

The value of an undefined symbol is treated in a special way.  If it is 0 then the symbol is not defined in this assembler source file, and ld tries to determine its value from other files linked into the same program.  You make this kind of symbol simply by mentioning a symbol name without defining it.  A non-zero value represents a .comm common declaration.  The value is how much common storage to reserve, in bytes (addresses).  The symbol refers to the first address of the allocated storage.


Type
Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes

Type

The type attribute of a symbol contains relocation (section) information, any flag settings indicating that a symbol is external, and (optionally), other information for linkers and debuggers.  The exact format depends on the object-code output format in use.


Symbol Attributes: a.out
Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes

Symbol Attributes: a.out

* Menu:

Symbol Desc	Descriptor

Symbol Other	Other


Descriptor
Node: Symbol Desc, Next: Symbol Other, Prev: , Up: a.out Symbols

Descriptor

This is an arbitrary 16-bit value.  You may establish a symbol's descriptor value by using a .desc statement (see .desc).  A descriptor value means nothing to as.


Other
Node: Symbol Other, Next: , Prev: Symbol Desc, Up: a.out Symbols

Other

This is an arbitrary 8-bit value.  It means nothing to as.


Symbol Attributes for COFF
Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes

Symbol Attributes for COFF

The COFF format supports a multitude of auxiliary symbol attributes; like the primary symbol attributes, they are set between .def and .endef directives.

Primary Attributes

The symbol name is set with .def; the value and type, respectively, with .val and .type.

Auxiliary Attributes

The as directives .dim, .line, .scl, .size, and .tag can generate auxiliary symbol table information for COFF.


Symbol Attributes for SOM
Node: SOM Symbols, Next: , Prev: COFF Symbols, Up: Symbol Attributes

Symbol Attributes for SOM

The SOM format for the HPPA supports a multitude of symbol attributes set with the .EXPORT and .IMPORT directives.

The attributes are described in HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) under the IMPORT and EXPORT assembler directive documentation.


Expressions
Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top

Expressions

An "expression" specifies an address or numeric value.  Whitespace may precede and/or follow an expression.

The result of an expression must be an absolute number, or else an offset into a particular section.  If an expression is not absolute, and there is not enough information when as sees the expression to know its section, a second pass over the source program might be necessary to interpret the expression--but the second pass is currently not implemented.  as aborts with an error message in this situation.

* Menu:

Empty Exprs	Empty Expressions

Integer Exprs	Integer Expressions


Empty Expressions
Node: Empty Exprs, Next: Integer Exprs, Prev: , Up: Expressions

Empty Expressions

An empty expression has no value: it is just whitespace or null.  Wherever an absolute expression is required, you may omit the expression, and as assumes a value of (absolute) 0.  This is compatible with other assemblers.


Integer Expressions
Node: Integer Exprs, Next: , Prev: Empty Exprs, Up: Expressions

Integer Expressions

An "integer expression" is one or more arguments delimited by operators.

* Menu:

Arguments	Arguments

Operators	Operators

Prefix Ops	Prefix Operators

Infix Ops	Infix Operators


Arguments
Node: Arguments, Next: Operators, Prev: , Up: Integer Exprs

Arguments

"Arguments" are symbols, numbers or subexpressions.  In other contexts arguments are sometimes called "arithmetic operands".  In this manual, to avoid confusing them with the "instruction operands" of the machine language, we use the term "argument" to refer to parts of expressions only, reserving the word "operand" to refer only to machine instruction operands.

Symbols are evaluated to yield {section NNN} where section is one of text, data, bss, absolute, or undefined.  NNN is a signed, 2's complement 32 bit integer.

Numbers are usually integers.

A number can be a flonum or bignum.  In this case, you are warned that only the low order 32 bits are used, and as pretends these 32 bits are an integer.  You may write integer-manipulating instructions that act on exotic constants, compatible with other assemblers.

Subexpressions are a left parenthesis ( followed by an integer expression, followed by a right parenthesis ); or a prefix operator followed by an argument.


Operators
Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs

Operators

"Operators" are arithmetic functions, like + or %.  Prefix operators are followed by an argument.  Infix operators appear between their arguments.  Operators may be preceded and/or followed by whitespace.


Prefix Operator
Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs

Prefix Operator

as has the following "prefix operators".  They each take one argument, which must be absolute.

-

"Negation".  Two's complement negation.

~

"Complementation".  Bitwise not.


Infix Operators
Node: Infix Ops, Next: , Prev: Prefix Ops, Up: Integer Exprs

Infix Operators

"Infix operators" take two arguments, one on either side.  Operators have precedence, but operations with equal precedence are performed left to right.  Apart from + or -, both arguments must be absolute, and the result is absolute.

1.	Highest Precedence

*

"Multiplication".

/

"Division".  Truncation is the same as the C operator /

%

"Remainder".

<

<<

"Shift Left".  Same as the C operator <<.

>

>>

"Shift Right".  Same as the C operator >>.

2.	Intermediate precedence

|

"Bitwise Inclusive Or".

&

"Bitwise And".

^

"Bitwise Exclusive Or".

!

"Bitwise Or Not".

3.	Lowest Precedence

+

"Addition".  If either argument is absolute, the result has the section of the other argument.  You may not add together arguments from different sections.

-

"Subtraction".  If the right argument is absolute, the result has the section of the left argument.  If both arguments are in the same section, the result is absolute.  You may not subtract arguments from different sections.

In short, it's only meaningful to add or subtract the offsets in an address; you can only have a defined section in one of the two arguments.


Assembler Directives
Node: Pseudo Ops, Next: Machine Dependencies, Prev: Expressions, Up: Top

Assembler Directives

All assembler directives have names that begin with a period (.).  The rest of the name is letters, usually in lower case.

This chapter discusses directives that are available regardless of the target machine configuration for the GNU assembler.  Some machine configurations provide additional directives.  See Machine Dependencies.

* Menu:

Abort	.abort

ABORT	.ABORT

Align	.align abs-expr , abs-expr

App-File	.app-file string

Ascii	.ascii "string"...

Asciz	.asciz "string"...

Balign	.balign abs-expr , abs-expr

Byte	.byte expressions

Comm	.comm symbol , length

Data	.data subsection

Def	.def name

Desc	.desc symbol, abs-expression

Dim	.dim

Double	.double flonums

Eject	.eject

Else	.else

Endef	.endef

Endif	.endif

Equ	.equ symbol, expression

Equiv	.equiv symbol, expression

Err	.err

Extern	.extern

File	.file string

Fill	.fill repeat , size , value

Float	.float flonums

Global	.global symbol, .globl symbol

hword	.hword expressions

Ident	.ident

If	.if absolute expression

Include	.include "file"

Int	.int expressions

Irp	.irp symbol,values...

Irpc	.irpc symbol,values...

Lcomm	.lcomm symbol , length

Lflags	.lflags

Line	.line line-number

Ln	.ln line-number

Linkonce	.linkonce [type]

List	.list

Long	.long expressions

Macro	.macro name args...

MRI	.mri val

Nolist	.nolist

Octa	.octa bignums

Org	.org new-lc , fill

P2align	.p2align abs-expr , abs-expr

Psize	.psize lines, columns

Quad	.quad bignums

Rept	.rept count

Sbttl	.sbttl "subheading"

Scl	.scl class

Section	.section name, subsection

Set	.set symbol, expression

Short	.short expressions

Single	.single flonums

Size	.size

Skip	.skip size , fill

Sleb128	.sleb128 expressions

Space	.space size , fill

Stab	.stabd, .stabn, .stabs

String	.string "str"

Symver	.symver name,name2@nodename

Tag	.tag structname

Text	.text subsection

Title	.title "heading"

Type	.type int

Val	.val addr

Uleb128	.uleb128 expressions

Word	.word expressions

Deprecated	Deprecated Directives


.abort
Node: Abort, Next: ABORT, Prev: , Up: Pseudo Ops

.abort

This directive stops the assembly immediately.  It is for compatibility with other assemblers.  The original idea was that the assembly language source would be piped into the assembler.  If the sender of the source quit, it could use this directive tells as to quit also.  One day .abort will not be supported.


.ABORT
Node: ABORT, Next: Align, Prev: Abort, Up: Pseudo Ops

.ABORT

When producing COFF output, as accepts this directive as a synonym for .abort.

When producing b.out output, as accepts this directive, but ignores it.


.align abs-expr, abs-expr, abs-expr
Node: Align, Next: App-File, Prev: ABORT, Up: Pseudo Ops

.align abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary.  The first expression (which must be absolute) is the alignment required, as described below.

The second expression (also absolute) gives the fill value to be stored in the padding bytes.  It (and the comma) may be omitted.  If it is omitted, the padding bytes are normally zero.  However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional.  If it is present, it is the maximum number of bytes that should be skipped by this alignment directive.  If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all.  You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The way the required alignment is specified varies from system to system.  For the a29k, hppa, m68k, m88k, w65, sparc, and Hitachi SH, and i386 using ELF format, the first expression is the alignment request in bytes.  For example .align 8 advances the location counter until it is a multiple of 8.  If the location counter is already a multiple of 8, no change is needed.

For other systems, including the i386 using a.out format, it is the number of low-order zero bits the location counter must have after advancement.  For example .align 3 advances the location counter until it a multiple of 8.  If the location counter is already a multiple of 8, no change is needed.

This inconsistency is due to the different behaviors of the various native assemblers for these systems which GAS must emulate.  GAS also provides .balign and .p2align directives, described later, which have a consistent behavior across all architectures (but are specific to GAS).


.app-file string
Node: App-File, Next: Ascii, Prev: Align, Up: Pseudo Ops

.app-file string

.app-file (which may also be spelled .file) tells as that we are about to start a new logical file.  string is the new file name.  In general, the filename is recognized whether or not it is surrounded by quotes "; but if you wish to specify an empty file name is permitted, you must give the quotes-"".  This statement may go away in future: it is only recognized to be compatible with old as programs.


.ascii "string"...
Node: Ascii, Next: Asciz, Prev: App-File, Up: Pseudo Ops

.ascii "string"...

.ascii expects zero or more string literals (see Strings) separated by commas.  It assembles each string (with no automatic trailing zero byte) into consecutive addresses.


.asciz "string"...
Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops

.asciz "string"...

.asciz is just like .ascii, but each string is followed by a zero byte.  The "z" in .asciz stands for "zero".


.balign[wl] abs-expr, abs-expr, abs-expr
Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops

.balign[wl] abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary.  The first expression (which must be absolute) is the alignment request in bytes.  For example .balign 8 advances the location counter until it is a multiple of 8.  If the location counter is already a multiple of 8, no change is needed.

The second expression (also absolute) gives the fill value to be stored in the padding bytes.  It (and the comma) may be omitted.  If it is omitted, the padding bytes are normally zero.  However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional.  If it is present, it is the maximum number of bytes that should be skipped by this alignment directive.  If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all.  You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The .balignw and .balignl directives are variants of the .balign directive.  The .balignw directive treats the fill pattern as a two byte word value.  The .balignl directives treats the fill pattern as a four byte longword value.  For example, .balignw 4,0x368d will align to a multiple of 4.  If it skips two bytes, they will be filled in with the value 0x368d (the exact placement of the bytes depends upon the endianness of the processor).  If it skips 1 or 3 bytes, the fill value is undefined.


.byte expressions
Node: Byte, Next: Comm, Prev: Balign, Up: Pseudo Ops

.byte expressions

.byte expects zero or more expressions, separated by commas.  Each expression is assembled into the next byte.


.comm symbol, length
Node: Comm, Next: Data, Prev: Byte, Up: Pseudo Ops

.comm symbol , length

.comm declares a common symbol named symbol.  When linking, a common symbol in one object file may be merged with a defined or common symbol of the same name in another object file.  If ld does not see a definition for the symbol-just one or more common symbols-then it will allocate length bytes of uninitialized memory.  length must be an absolute expression.  If ld sees multiple common symbols with the same name, and they do not all have the same size, it will allocate space using the largest size.

When using ELF, the .comm directive takes an optional third argument.  This is the desired alignment of the symbol, specified as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero).  The alignment must be an absolute expression, and it must be a power of two.  If ld allocates uninitialized memory for the common symbol, it will use the alignment when placing the symbol.  If no alignment is specified, as will set the alignment to the largest power of two less than or equal to the size of the symbol, up to a maximum of 16.

The syntax for .comm differs slightly on the HPPA.  The syntax is symbol .comm, length; symbol is optional.


.data subsection
Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops

.data subsection

.data tells as to assemble the following statements onto the end of the data subsection numbered subsection (which is an absolute expression).  If subsection is omitted, it defaults to zero.


.def name
Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops

.def name

Begin defining debugging information for a symbol name; the definition extends until the .endef directive is encountered.

This directive is only observed when as is configured for COFF format output; when producing b.out, .def is recognized, but ignored.


.desc symbol, abs-expression
Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops

.desc symbol, abs-expression

This directive sets the descriptor of the symbol (see Symbol Attributes) to the low 16 bits of an absolute expression.

The .desc directive is not available when as is configured for COFF output; it is only for a.out or b.out object format.  For the sake of compatibility, as accepts it, but produces no output, when configured for COFF.


.dim
Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops

.dim

This directive is generated by compilers to include auxiliary debugging information in the symbol table.  It is only permitted inside .def/.endef pairs.

.dim is only meaningful when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.


.double flonums
Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops

.double flonums

.double expects zero or more flonums, separated by commas.  It assembles floating point numbers.  The exact kind of floating point numbers emitted depends on how as is configured.  See Machine Dependencies.


.eject
Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops

.eject

Force a page break at this point, when generating assembly listings.


.else
Node: Else, Next: Endef, Prev: Eject, Up: Pseudo Ops

.else

.else is part of the as support for conditional assembly; see .if.  It marks the beginning of a section of code to be assembled if the condition for the preceding .if was false.


.endef
Node: Endef, Next: Endif, Prev: Else, Up: Pseudo Ops

.endef

This directive flags the end of a symbol definition begun with .def.

.endef is only meaningful when generating COFF format output; if as is configured to generate b.out, it accepts this directive but ignores it.


.endif
Node: Endif, Next: Equ, Prev: Endef, Up: Pseudo Ops

.endif

.endif is part of the as support for conditional assembly; it marks the end of a block of code that is only assembled conditionally.  See .if.


.equ symbol, expression
Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops

.equ symbol, expression

This directive sets the value of symbol to expression.  It is synonymous with .set; see .set.

The syntax for equ on the HPPA is symbol .equ expression.


.equiv symbol, expression
Node: Equiv, Next: Err, Prev: Equ, Up: Pseudo Ops

.equiv symbol, expression

The .equiv directive is like .equ and .set, except that the assembler will signal an error if symbol is already defined.

Except for the contents of the error message, this is roughly equivalent to

.ifdef SYM
.err
.endif
.equ SYM,VAL


.err
Node: Err, Next: Extern, Prev: Equiv, Up: Pseudo Ops

.err

If as assembles a .err directive, it will print an error message and, unless the -Z option was used, it will not generate an object file.  This can be used to signal error an conditionally compiled code.


.extern
Node: Extern, Next: File, Prev: Err, Up: Pseudo Ops

.extern

.extern is accepted in the source program--for compatibility with other assemblers--but it is ignored.  as treats all undefined symbols as external.


.file string
Node: File, Next: Fill, Prev: Extern, Up: Pseudo Ops

.file string

.file (which may also be spelled .app-file) tells as that we are about to start a new logical file.  string is the new file name.  In general, the filename is recognized whether or not it is surrounded by quotes "; but if you wish to specify an empty file name, you must give the quotes-"".  This statement may go away in future: it is only recognized to be compatible with old as programs.  In some configurations of as, .file has already been removed to avoid conflicts with other assemblers.  See Machine Dependencies.


.fill repeat, size, value
Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops

.fill repeat , size , value

result, size and value are absolute expressions.  This emits repeat copies of size bytes.  Repeat may be zero or more.  Size may be zero or more, but if it is more than 8, then it is deemed to have the value 8, compatible with other people's assemblers.  The contents of each repeat bytes is taken from an 8-byte number.  The highest order 4 bytes are zero.  The lowest order 4 bytes are value rendered in the byte-order of an integer on the computer as is assembling for.  Each size bytes in a repetition is taken from the lowest order size bytes of this number.  Again, this bizarre behavior is compatible with other people's assemblers.

size and value are optional.  If the second comma and value are absent, value is assumed zero.  If the first comma and following tokens are absent, size is assumed to be 1.


.float flonums
Node: Float, Next: Global, Prev: Fill, Up: Pseudo Ops

.float flonums

This directive assembles zero or more flonums, separated by commas.  It has the same effect as .single.  The exact kind of floating point numbers emitted depends on how as is configured.  See Machine Dependencies.


.global symbol, .globl symbol
Node: Global, Next: hword, Prev: Float, Up: Pseudo Ops

.global symbol, .globl symbol

.global makes the symbol visible to ld.  If you define symbol in your partial program, its value is made available to other partial programs that are linked with it.  Otherwise, symbol takes its attributes from a symbol of the same name from another file linked into the same program.

Both spellings (.globl and .global) are accepted, for compatibility with other assemblers.

On the HPPA, .global is not always enough to make it accessible to other partial programs.  You may need the HPPA-only .EXPORT directive as well.  See HPPA Assembler Directives.


.hword expressions
Node: hword, Next: Ident, Prev: Global, Up: Pseudo Ops

.hword expressions

This expects zero or more expressions, and emits a 16 bit number for each.

This directive is a synonym for .short; depending on the target architecture, it may also be a synonym for .word.


.ident
Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops

.ident

This directive is used by some assemblers to place tags in object files.  as simply accepts the directive for source-file compatibility with such assemblers, but does not actually emit anything for it.


.if absolute expression
Node: If, Next: Include, Prev: Ident, Up: Pseudo Ops

.if absolute expression

.if marks the beginning of a section of code which is only considered part of the source program being assembled if the argument (which must be an absolute expression) is non-zero.  The end of the conditional section of code must be marked by .endif (see .endif); optionally, you may include code for the alternative condition, flagged by .else (see .else).

The following variants of .if are also supported:

.ifdef symbol

Assembles the following section of code if the specified symbol has been defined.

.ifndef symbol

.ifnotdef symbol

Assembles the following section of code if the specified symbol has not been defined.  Both spelling variants are equivalent.


.include "file"
Node: Include, Next: Int, Prev: If, Up: Pseudo Ops

.include "file"

This directive provides a way to include supporting files at specified points in your source program.  The code from file is assembled as if it followed the point of the .include; when the end of the included file is reached, assembly of the original file continues.  You can control the search paths used with the -I command-line option (see Command-Line Options).  Quotation marks are required around file.


.int expressions
Node: Int, Next: Irp, Prev: Include, Up: Pseudo Ops

.int expressions

Expect zero or more expressions, of any section, separated by commas.  For each expression, emit a number that, at run time, is the value of that expression.  The byte order and bit size of the number depends on what kind of target the assembly is for.


.irp symbol,values...
Node: Irp, Next: Irpc, Prev: Int, Up: Pseudo Ops

.irp symbol,values...

Evaluate a sequence of statements assigning different values to symbol.  The sequence of statements starts at the .irp directive, and is terminated by an .endr directive.  For each value, symbol is set to value, and the sequence of statements is assembled.  If no value is listed, the sequence of statements is assembled once, with symbol set to the null string.  To refer to symbol within the sequence of statements, use \symbol.

For example, assembling

        .irp    param,1,2,3
        move    d\param,sp@-
        .endr

is equivalent to assembling

        move    d1,sp@-
        move    d2,sp@-
        move    d3,sp@-


.irpc symbol,values...
Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops

.irpc symbol,values...

Evaluate a sequence of statements assigning different values to symbol.  The sequence of statements starts at the .irpc directive, and is terminated by an .endr directive.  For each character in value, symbol is set to the character, and the sequence of statements is assembled.  If no value is listed, the sequence of statements is assembled once, with symbol set to the null string.  To refer to symbol within the sequence of statements, use \symbol.

For example, assembling

        .irpc    param,123
        move    d\param,sp@-
        .endr

is equivalent to assembling

        move    d1,sp@-
        move    d2,sp@-
        move    d3,sp@-


.lcomm symbol, length
Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops

.lcomm symbol , length

Reserve length (an absolute expression) bytes for a local common denoted by symbol.  The section and value of symbol are those of the new local common.  The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed.  Symbol is not declared global (see .global), so is normally not visible to ld.

Some targets permit a third argument to be used with .lcomm.  This argument specifies the desired alignment of the symbol in the bss section.

The syntax for .lcomm differs slightly on the HPPA.  The syntax is symbol .lcomm, length; symbol is optional.


.lflags
Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops

.lflags

as accepts this directive, for compatibility with other assemblers, but ignores it.


.line line-number
Node: Line, Next: Ln, Prev: Lflags, Up: Pseudo Ops

.line line-number

Change the logical line number.  line-number must be an absolute expression.  The next line has that logical line number.  Therefore any other statements on the current line (after a statement separator character) are reported as on logical line number line-number - 1.  One day as will no longer support this directive: it is recognized only for compatibility with existing assembler programs.

Warning: In the AMD29K configuration of as, this command is not available; use the synonym .ln in that context.

Even though this is a directive associated with the a.out or b.out object-code formats, as still recognizes it when producing COFF output, and treats .line as though it were the COFF .ln if it is found outside a .def/.endef pair.

Inside a .def, .line is, instead, one of the directives used by compilers to generate auxiliary symbol information for debugging.


.linkonce [type]
Node: Linkonce, Next: List, Prev: Ln, Up: Pseudo Ops

.linkonce [type]

Mark the current section so that the linker only includes a single copy of it.  This may be used to include the same section in several different object files, but ensure that the linker will only include it once in the final output file.  The .linkonce pseudo-op must be used for each instance of the section.  Duplicate sections are detected based on the section name, so it should be unique.

This directive is only supported by a few object file formats; as of this writing, the only object file format which supports it is the Portable Executable format used on Windows NT.

The type argument is optional.  If specified, it must be one of the following strings.  For example:

.linkonce same_size

Not all types may be supported on all object file formats.

discard

Silently discard duplicate sections.  This is the default.

one_only

Warn if there are duplicate sections, but still keep only one copy.

same_size

Warn if any of the duplicates have different sizes.

same_contents

Warn if any of the duplicates do not have exactly the same contents.


.ln line-number
Node: Ln, Next: Linkonce, Prev: Line, Up: Pseudo Ops

.ln line-number

.ln is a synonym for .line.


.mri val
Node: MRI, Next: Nolist, Prev: Macro, Up: Pseudo Ops

.mri val

If val is non-zero, this tells as to enter MRI mode.  If val is zero, this tells as to exit MRI mode.  This change affects code assembled until the next .mri directive, or until the end of the file.  See MRI mode.


.list
Node: List, Next: Long, Prev: Linkonce, Up: Pseudo Ops

.list

Control (in conjunction with the .nolist directive) whether or not assembly listings are generated.  These two directives maintain an internal counter (which is zero initially).   .list increments the counter, and .nolist decrements it.  Assembly listings are generated whenever the counter is greater than zero.

By default, listings are disabled.  When you enable them (with the -a command line option; see Command-Line Options), the initial value of the listing counter is one.


.long expressions
Node: Long, Next: Macro, Prev: List, Up: Pseudo Ops

.long expressions

.long is the same as .int, see .int.


.macro
Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops

.macro

The commands .macro and .endm allow you to define macros that generate assembly output.  For example, this definition specifies a macro sum that puts a sequence of numbers into memory:

        .macro  sum from=0, to=5
        .long   \from
        .if     \to-\from
        sum     "(\from+1)",\to
        .endif
        .endm

With that definition, SUM 0,5 is equivalent to this assembly input:

        .long   0
        .long   1
        .long   2
        .long   3
        .long   4
        .long   5

.macro macname

.macro macname macargs ...

Begin the definition of a macro called macname.  If your macro definition requires arguments, specify their names after the macro name, separated by commas or spaces.  You can supply a default value for any macro argument by following the name with =deflt.  For example, these are all valid .macro statements:

.macro comm

Begin the definition of a macro called comm, which takes no arguments.

.macro plus1 p, p1

.macro plus1 p p1

Either statement begins the definition of a macro called plus1, which takes two arguments; within the macro definition, write \p or \p1 to evaluate the arguments.

.macro reserve_str p1=0 p2

Begin the definition of a macro called reserve_str, with two arguments.  The first argument has a default value, but not the second.  After the definition is complete, you can call the macro either as reserve_str a,b (with \p1 evaluating to a and \p2 evaluating to b), or as reserve_str ,b (with \p1 evaluating as the default, in this case 0, and \p2 evaluating to b).

When you call a macro, you can specify the argument values either by position, or by keyword.  For example, sum 9,17 is equivalent to sum to=17, from=9.

.endm

Mark the end of a macro definition.

.exitm

Exit early from the current macro definition.

\@

{No Value For "\li720{}AS"} maintains a counter of how many macros it has executed in this pseudo-variable; you can copy that number to your output with \@, but only within a macro definition.


.nolist
Node: Nolist, Next: Octa, Prev: MRI, Up: Pseudo Ops

.nolist

Control (in conjunction with the .list directive) whether or not assembly listings are generated.  These two directives maintain an internal counter (which is zero initially).   .list increments the counter, and .nolist decrements it.  Assembly listings are generated whenever the counter is greater than zero.


.octa bignums
Node: Octa, Next: Org, Prev: Nolist, Up: Pseudo Ops

.octa bignums

This directive expects zero or more bignums, separated by commas.  For each bignum, it emits a 16-byte integer.

The term "octa" comes from contexts in which a "word" is two bytes; hence octa-word for 16 bytes.


.org new-lc, fill
Node: Org, Next: P2align, Prev: Octa, Up: Pseudo Ops

.org new-lc , fill

Advance the location counter of the current section to new-lc.  new-lc is either an absolute expression or an expression with the same section as the current subsection.  That is, you can't use .org to cross sections: if new-lc has the wrong section, the .org directive is ignored.  To be compatible with former assemblers, if the section of new-lc is absolute, as issues a warning, then pretends the section of new-lc is the same as the current subsection.

.org may only increase the location counter, or leave it unchanged; you cannot use .org to move the location counter backwards.

Because as tries to assemble programs in one pass, new-lc may not be undefined.  If you really detest this restriction we eagerly await a chance to share your improved assembler.

Beware that the origin is relative to the start of the section, not to the start of the subsection.  This is compatible with other people's assemblers.

When the location counter (of the current subsection) is advanced, the intervening bytes are filled with fill which should be an absolute expression.  If the comma and fill are omitted, fill defaults to zero.


.p2align[wl] abs-expr, abs-expr, abs-expr
Node: P2align, Next: Psize, Prev: Org, Up: Pseudo Ops

.p2align[wl] abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary.  The first expression (which must be absolute) is the number of low-order zero bits the location counter must have after advancement.  For example .p2align 3 advances the location counter until it a multiple of 8.  If the location counter is already a multiple of 8, no change is needed.

The second expression (also absolute) gives the fill value to be stored in the padding bytes.  It (and the comma) may be omitted.  If it is omitted, the padding bytes are normally zero.  However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional.  If it is present, it is the maximum number of bytes that should be skipped by this alignment directive.  If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all.  You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The .p2alignw and .p2alignl directives are variants of the .p2align directive.  The .p2alignw directive treats the fill pattern as a two byte word value.  The .p2alignl directives treats the fill pattern as a four byte longword value.  For example, .p2alignw 2,0x368d will align to a multiple of 4.  If it skips two bytes, they will be filled in with the value 0x368d (the exact placement of the bytes depends upon the endianness of the processor).  If it skips 1 or 3 bytes, the fill value is undefined.


.psize lines, columns
Node: Psize, Next: Quad, Prev: P2align, Up: Pseudo Ops

.psize lines , columns

Use this directive to declare the number of lines--and, optionally, the number of columns--to use for each page, when generating listings.

If you do not use .psize, listings use a default line-count of 60.  You may omit the comma and columns specification; the default width is 200 columns.

{No Value For "rd{}AS"} generates formfeeds whenever the specified number of lines is exceeded (or whenever you explicitly request one, using .eject).

If you specify lines as 0, no formfeeds are generated save those explicitly specified with .eject.


.quad bignums
Node: Quad, Next: Rept, Prev: Psize, Up: Pseudo Ops

.quad bignums

.quad expects zero or more bignums, separated by commas.  For each bignum, it emits an 8-byte integer.  If the bignum won't fit in 8 bytes, it prints a warning message; and just takes the lowest order 8 bytes of the bignum.  The term "quad" comes from contexts in which a "word" is two bytes; hence quad-word for 8 bytes.


.rept count
Node: Rept, Next: Sbttl, Prev: Quad, Up: Pseudo Ops

.rept count

Repeat the sequence of lines between the .rept directive and the next .endr directive count times.

For example, assembling

        .rept   3
        .long   0
        .endr

is equivalent to assembling

        .long   0
        .long   0
        .long   0


.sbttl "subheading"
Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops

.sbttl "subheading"

Use subheading as the title (third line, immediately after the title line) when generating assembly listings.

This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.


.scl class
Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops

.scl class

Set the storage-class value for a symbol.  This directive may only be used inside a .def/.endef pair.  Storage class may flag whether a symbol is static or external, or it may record further symbolic debugging information.

The .scl directive is primarily associated with COFF output; when configured to generate b.out output format, as accepts this directive but ignores it.


.section name
Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops

.section name

Use the .section directive to assemble the following code into a section named name.

This directive is only supported for targets that actually support arbitrarily named sections; on a.out targets, for example, it is not accepted, even with a standard a.out section name.

For COFF targets, the .section directive is used in one of the following ways:

.section name[, "flags"]
.section name[, subsegment]

If the optional argument is quoted, it is taken as flags to use for the section.  Each flag is a single character.  The following flags are recognized:

b

bss section (uninitialized data)

n

section is not loaded

w

writable section

d

data section

r

read-only section

x

executable section

If no flags are specified, the default flags depend upon the section name.  If the section name is not recognized, the default will be for the section to be loaded and writable.

If the optional argument to the .section directive is not quoted, it is taken as a subsegment number (see Sub-Sections).

For ELF targets, the .section directive is used like this:

.section name[, "flags"[, @type]]

The optional flags argument is a quoted string which may contain any combintion of the following characters:

a

section is allocatable

w

section is writable

x

section is executable

The optional type argument may contain one of the following constants:

@progbits

section contains data

@nobits

section does not contain data (i.e., section only occupies space)

If no flags are specified, the default flags depend upon the section name.  If the section name is not recognized, the default will be for the section to have none of the above flags: it will not be allocated in memory, nor writable, nor executable.  The section will contain data.

For ELF targets, the assembler supports another type of .section directive for compatibility with the Solaris assembler:

.section "name"[, flags...]

Note that the section name is quoted.  There may be a sequence of comma separated flags:

#alloc

section is allocatable

#write

section is writable

#execinstr

section is executable


.set symbol, expression
Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops

.set symbol, expression

Set the value of symbol to expression.  This changes symbol's value and type to conform to expression.  If symbol was flagged as external, it remains flagged (see Symbol Attributes).

You may .set a symbol many times in the same assembly.

If you .set a global symbol, the value stored in the object file is the last value stored into it.

The syntax for set on the HPPA is symbol .set expression.


.short expressions
Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops

.short expressions

.short is normally the same as .word.  See .word.

In some configurations, however, .short and .word generate numbers of different lengths; see Machine Dependencies.


.single flonums
Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops

.single flonums

This directive assembles zero or more flonums, separated by commas.  It has the same effect as .float.  The exact kind of floating point numbers emitted depends on how as is configured.  See Machine Dependencies.


.size
Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops

.size

This directive is generated by compilers to include auxiliary debugging information in the symbol table.  It is only permitted inside .def/.endef pairs.

.size is only meaningful when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.


.sleb128 expressions
Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops

.sleb128 expressions

sleb128 stands for "signed little endian base 128."  This is a compact, variable length representation of numbers used by the DWARF symbolic debugging format.  See .uleb128.


.skip size, fill
Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops

.skip size , fill

This directive emits size bytes, each of value fill.  Both size and fill are absolute expressions.  If the comma and fill are omitted, fill is assumed to be zero.  This is the same as .space.


.space size, fill
Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops

.space size , fill

This directive emits size bytes, each of value fill.  Both size and fill are absolute expressions.  If the comma and fill are omitted, fill is assumed to be zero.  This is the same as .skip.

Warning: .space has a completely different meaning for HPPA targets; use .block as a substitute.  See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for the meaning of the .space directive.  See HPPA Assembler Directives, for a summary.

On the AMD 29K, this directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: In most versions of the GNU assembler, the directive .space has the effect of .block  See Machine Dependencies.


.stabd, .stabn, .stabs
Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops

.stabd, .stabn, .stabs

There are three directives that begin .stab.  All emit symbols (see Symbols), for use by symbolic debuggers.  The symbols are not entered in the as hash table: they cannot be referenced elsewhere in the source file.  Up to five fields are required:

string

This is the symbol's name.  It may contain any character except \000, so is more general than ordinary symbol names.  Some debuggers used to code arbitrarily complex structures into symbol names using this field.

type

An absolute expression.  The symbol's type is set to the low 8 bits of this expression.  Any bit pattern is permitted, but ld and debuggers choke on silly bit patterns.

other

An absolute expression.  The symbol's "other" attribute is set to the low 8 bits of this expression.

desc

An absolute expression.  The symbol's descriptor is set to the low 16 bits of this expression.

value

An absolute expression which becomes the symbol's value.

If a warning is detected while reading a .stabd, .stabn, or .stabs statement, the symbol has probably already been created; you get a half-formed symbol in your object file.  This is compatible with earlier assemblers!

.stabd type , other , desc

The "name" of the symbol generated is not even an empty string.  It is a null pointer, for compatibility.  Older assemblers used a null pointer so they didn't waste space in object files with empty strings.

The symbol's value is set to the location counter, relocatably.  When your program is linked, the value of this symbol is the address of the location counter when the .stabd was assembled.

.stabn type , other , desc , value

The name of the symbol is set to the empty string "".

.stabs string ,  type , other , desc , value

All five fields are specified.


.string"str"
Node: String, Next: Symver, Prev: Stab, Up: Pseudo Ops

.string "str"

Copy the characters in str to the object file.  You may specify more than one string to copy, separated by commas.  Unless otherwise specified for a particular machine, the assembler marks the end of each string with a 0 byte.  You can use any of the escape sequences described in Strings.


.symver
Node: Symver, Next: Tag, Prev: String, Up: Pseudo Ops

.symver

Use the .symver directive to bind symbols to specific version nodes within a source file.  This is only supported on ELF platforms, and is typically used when assembling files to be linked into a shared library.  There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library.

For ELF targets, the .symver directive is used like this:

.symver name, name2@nodename

In this case, the symbol name must exist and be defined within the file being assembled.  The .versym directive effectively creates a symbol alias with the name name2@nodename, and in fact the main reason that we just don't try and create a regular alias is that the @ character isn't permitted in symbol names.  The name2 part of the name is the actual name of the symbol by which it will be externally referenced.  The name name itself is merely a name of convenience that is used so that it is possible to have definitions for multiple versions of a function within a single source file, and so that the compiler can unambiguously know which version of a function is being mentioned.  The nodename portion of the alias should be the name of a node specified in the version script supplied to the linker when building a shared library.  If you are attempting to override a versioned symbol from a shared library, then nodename should correspond to the nodename of the symbol you are trying to override.


.tag structname
Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops

.tag structname

This directive is generated by compilers to include auxiliary debugging information in the symbol table.  It is only permitted inside .def/.endef pairs.  Tags are used to link structure definitions in the symbol table with instances of those structures.

.tag is only used when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.


.text subsection
Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops

.text subsection

Tells as to assemble the following statements onto the end of the text subsection numbered subsection, which is an absolute expression.  If subsection is omitted, subsection number zero is used.


.title "heading"
Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops

.title "heading"

Use heading as the title (second line, immediately after the source file name and pagenumber) when generating assembly listings.

This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.


.type int
Node: Type, Next: Val, Prev: Title, Up: Pseudo Ops

.type int

This directive, permitted only within .def/.endef pairs, records the integer int as the type attribute of a symbol table entry.

.type is associated only with COFF format output; when as is configured for b.out output, it accepts this directive but ignores it.


.val addr
Node: Val, Next: Uleb128, Prev: Type, Up: Pseudo Ops

.val addr

This directive, permitted only within .def/.endef pairs, records the address addr as the value attribute of a symbol table entry.

.val is used only for COFF output; when as is configured for b.out, it accepts this directive but ignores it.


.uleb128 expressions
Node: Uleb128, Next: Word, Prev: Val, Up: Pseudo Ops

.uleb128 expressions

uleb128 stands for "unsigned little endian base 128."  This is a compact, variable length representation of numbers used by the DWARF symbolic debugging format.  See .sleb128.


.word expressions
Node: Word, Next: Deprecated, Prev: Uleb128, Up: Pseudo Ops

.word expressions

This directive expects zero or more expressions, of any section, separated by commas.

The size of the number emitted, and its byte order, depend on what target computer the assembly is for.

Warning: Special Treatment to support Compilers

Machines with a 32-bit address space, but that do less than 32-bit addressing, require the following special treatment.  If the machine of interest to you does 32-bit addressing (or doesn't require it; see Machine Dependencies), you can ignore this issue.

In order to assemble compiler output into something that works, as occasionlly does strange things to .word directives.  Directives of the form .word sym1-sym2 are often emitted by compilers as part of jump tables.  Therefore, when as assembles a directive of the form .word sym1-sym2, and the difference between sym1 and sym2 does not fit in 16 bits, as creates a "secondary jump table", immediately before the next label.  This secondary jump table is preceded by a short-jump to the first byte after the secondary table.  This short-jump prevents the flow of control from accidentally falling into the new table.  Inside the table is a long-jump to sym2.  The original .word contains sym1 minus the address of the long-jump to sym2.

If there were several occurrences of .word sym1-sym2 before the secondary jump table, all of them are adjusted.  If there was a .word sym3-sym4, that also did not fit in sixteen bits, a long-jump to sym4 is included in the secondary jump table, and the .word directives are adjusted to contain sym3 minus the address of the long-jump to sym4; and so on, for as many entries in the original jump table as necessary.


Deprecated Directives
Node: Deprecated, Next: , Prev: Word, Up: Pseudo Ops

Deprecated Directives

One day these directives won't work.  They are included for compatibility with older assemblers.

.abort

.app-file

.line


Machine Dependent Features
Node: Machine Dependencies, Next: Reporting Bugs, Prev: Pseudo Ops, Up: Top

Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs.  Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform.  Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set.  For details on that subject, see the hardware manufacturer's manual.

* Menu:

AMD29K-Dependent	AMD 29K Dependent Features

ARC-Dependent	ARC Dependent Features

ARM-Dependent	ARM Dependent Features

D10V-Dependent	D10V Dependent Features

H8/300-Dependent	Hitachi H8/300 Dependent Features

H8/500-Dependent	Hitachi H8/500 Dependent Features

HPPA-Dependent	HPPA Dependent Features

i386-Dependent	Intel 80386 Dependent Features

i960-Dependent	Intel 80960 Dependent Features

M32R-Dependent	M32R Dependent Features

M68K-Dependent	M680x0 Dependent Features

MIPS-Dependent	MIPS Dependent Features

SH-Dependent	Hitachi SH Dependent Features

Sparc-Dependent	SPARC Dependent Features

V850-Dependent	V850 Dependent Features

Z8000-Dependent	Z8000 Dependent Features

Vax-Dependent	VAX Dependent Features


ARC Dependent Features
Node: ARC-Dependent, Next: ARM-Dependent, Prev: AMD29K-Dependent, Up: Machine Dependencies

ARC Dependent Features

* Menu:

ARC-Opts	Options

ARC-Float	Floating Point

ARC-Directives	Sparc Machine Directives


Options
Node: ARC-Opts, Next: ARC-Float, Prev: , Up: ARC-Dependent

Options

The ARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.

By default, as assumes the core instruction set (ARC base).  The .cpu pseudo-op is intended to be used to select the variant.

-mbig-endian

-mlittle-endian

Any ARC configuration of as can select big-endian or little-endian output at run time (unlike most other GNU development tools, which must be configured for one or the other).  Use -mbig-endian to select big-endian output, and -mlittle-endian for little-endian.


Floating Point
Node: ARC-Float, Next: ARC-Directives, Prev: ARC-Opts, Up: ARC-Dependent

Floating Point

The ARC cpu family currently does not have hardware floating point support.  Software floating point support is provided by GCC and uses IEEE floating-point numbers.


ARC Machine Directives
Node: ARC-Directives, Next: , Prev: ARC-Float, Up: ARC-Dependent

ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.cpu

This must be followed by the desired cpu.  The ARC is intended to be customizable, .cpu is used to select the desired variant [though currently there are none].


AMD 29K Dependent Features
Node: AMD29K-Dependent, Next: ARC-Dependent, Prev: , Up: Machine Dependencies

AMD 29K Dependent Features

* Menu:

AMD29K Options	Options

AMD29K Syntax	Syntax

AMD29K Floating Point	Floating Point

AMD29K Directives	AMD 29K Machine Directives

AMD29K Opcodes	Opcodes


Options
Node: AMD29K Options, Next: AMD29K Syntax, Prev: , Up: AMD29K-Dependent

Options

as has no additional command-line options for the AMD 29K family.


Syntax
Node: AMD29K Syntax, Next: AMD29K Floating Point, Prev: AMD29K Options, Up: AMD29K-Dependent

Syntax

* Menu:

AMD29K-Macros	Macros

AMD29K-Chars	Special Characters

AMD29K-Regs	Register Names


Macros
Node: AMD29K-Macros, Next: AMD29K-Chars, Prev: , Up: AMD29K Syntax

Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification.  Normal as macros should still work.


Special Characters
Node: AMD29K-Chars, Next: AMD29K-Regs, Prev: AMD29K-Macros, Up: AMD29K Syntax

Special Characters

; is the line comment character.

The character ? is permitted in identifiers (but may not begin an identifier).


Register Names
Node: AMD29K-Regs, Next: , Prev: AMD29K-Chars, Up: AMD29K Syntax

Register Names

General-purpose registers are represented by predefined symbols of the form GRnnn (for global registers) or LRnnn (for local registers), where nnn represents a number between 0 and 127, written with no leading zeros.  The leading letters may be in either upper or lower case; for example, gr13 and LR7 are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with %% to flag the expression as a register number):

%%expression

--where expression must be an absolute expression evaluating to a number between 0 and 255.  The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, as understands the following protected special-purpose register names for the AMD 29K family:

  vab    chd    pc0
  ops    chc    pc1
  cps    rbp    pc2
  cfg    tmc    mmu
  cha    tmr    lru

These unprotected special-purpose register names are also recognized:

  ipc    alu    fpe
  ipa    bp     inte
  ipb    fc     fps
  q      cr     exop


Floating Point
Node: AMD29K Floating Point, Next: AMD29K Directives, Prev: AMD29K Syntax, Up: AMD29K-Dependent

Floating Point

The AMD 29K family uses IEEE floating-point numbers.


AMD 29K Machine Directives
Node: AMD29K Directives, Next: AMD29K Opcodes, Prev: AMD29K Floating Point, Up: AMD29K-Dependent

AMD 29K Machine Directives

.block size , fill

This directive emits size bytes, each of value fill.  Both size and fill are absolute expressions.  If the comma and fill are omitted, fill is assumed to be zero.

In other versions of the GNU assembler, this directive is called .space.

.cputype

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.file

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: in other versions of the GNU assembler, .file is used for the directive called .app-file in the AMD 29K support.

.line

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.sect

This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

.use section name

Establishes the section and subsection for the following code; section name may be one of .text, .data, .data1, or .lit.  With one of the first three section name options, .use is equivalent to the machine directive section name; the remaining case, .use .lit, is the same as .data 200.


Opcodes
Node: AMD29K Opcodes, Next: , Prev: AMD29K Directives, Up: AMD29K-Dependent

Opcodes

as implements all the standard AMD 29K opcodes.  No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.


ARM Dependent Features
Node: ARM-Dependent, Next: D10V-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies

ARM Dependent Features

* Menu:

ARM Options	Options

ARM Syntax	Syntax

ARM Floating Point	Floating Point

ARM Directives	ARM Machine Directives

ARM Opcodes	Opcodes


Options
Node: ARM Options, Next: ARM Syntax, Prev: , Up: ARM-Dependent

Options

-marm [2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|strongarm|strongarm110]

This option specifies the target processor.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.

-marmv [2|2a|3|3m|4|4t]

This option specifies the target architecture.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.

-mthumb

This option specifies that only Thumb instructions should be assembled.

-mall

This option specifies that any Arm or Thumb instruction should be assembled.

-mfpa [10|11]

This option specifies the floating point architecture in use on the target processor.

-mfpe-old

Do not allow the assemble of floating point multiple instructions.

-mno-fpu

Do not allow the assembly of any floating point instructions.

-mthumb-interwork

This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]

This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure.  Calling Standard.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.


Syntax
Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent

Syntax

* Menu:

ARM-Chars	Special Characters

ARM-Regs	Register Names


Special Characters
Node: ARM-Chars, Next: ARM-Regs, Prev: , Up: ARM Syntax

Special Characters

; is the line comment character.

*TODO* Explain about /data modifier on symbols.


Register Names
Node: ARM-Regs, Next: , Prev: ARM-Chars, Up: ARM Syntax

Register Names

*TODO* Explain about ARM register naming, and the predefined names.


Floating Point
Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent

Floating Point

The ARM family uses IEEE floating-point numbers.


ARM Machine Directives
Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent

ARM Machine Directives

.code [16|32]

This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb

This performs the same action as .code 16.

.arm

This performs the same action as .code 32.

.force_thumb

This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func

This directive specifies that the following symbol is the name of a Thumb encoded function.  This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.


Opcodes
Node: ARM Opcodes, Next: , Prev: ARM Directives, Up: ARM-Dependent

Opcodes

as implements all the standard ARM opcodes.

*TODO* Document the pseudo-ops (adr, nop)

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.


D10V Dependent Features
Node: D10V-Dependent, Next: H8/300-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies

D10V Dependent Features

* Menu:

D10V-Opts	D10V Options

D10V-Syntax	Syntax

D10V-Float	Floating Point

D10V-Opcodes	Opcodes


D10V Options
Node: D10V-Opts, Next: D10V-Syntax, Prev: , Up: D10V-Dependent

D10V Options

The Mitsubishi D10V version of as has a few machine dependent options.

-O

The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.


Syntax
Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent

Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.  The differences are detailed below.

* Menu:

D10V-Size	Size Modifiers

D10V-Subs	Sub-Instructions

D10V-Chars	Special Characters

D10V-Regs	Register Names

D10V-Addressing	Addressing Modes

D10V-Word	@WORD Modifier


Size Modifiers
Node: D10V-Size, Next: D10V-Subs, Prev: , Up: D10V-Syntax

Size Modifiers

The D10V version of as uses the instruction names in the D10V Architecture Manual.  However, the names in the manual are sometimes ambiguous.  There are instruction names that can assemble to a short or long form opcode.  How does the assembler pick the correct form?  as will always pick the smallest form if it can.  When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form.  If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it.  For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s   foo.  Objdump and GDB will always append .s or .l to instructions which have both short and long forms.


Sub-Instructions
Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax

Sub-Instructions

The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section.  Some of these instructions will be short-form or sub-instructions.  These sub-instructions can be packed into a single instruction.  The assembler will do this automatically.  It will also detect when it should not pack instructions.  For example, when a label is defined, the next instruction will never be packaged with the previous one.  Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid.  Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.


Special Characters
Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax

Special Characters

; and # are the line comment characters.  Sub-instructions may be executed in order, in reverse-order, or in parallel.  Instructions listed in the standard one-per-line format will be executed sequentially.  To specify the executing order, use the following symbols:

->

Sequential with instruction on the left first.

<-

Sequential with instruction on the right first.

||

Parallel The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line.  For example

abs       a1      ->      abs     r0

Execute these sequentially.  The instruction on the right is in the right container and is executed second.

abs       r0      <-      abs     a1

Execute these reverse-sequentially.  The instruction on the right is in the right container, and is executed first.

ld2w    r2,@r8+         ||      mac     a0,r0,r7

Execute these in parallel.

ld2w    r2,@r8+         ||

mac     a0,r0,r7

Two-line format. Execute these in parallel.

ld2w    r2,@r8+

mac     a0,r0,r7

Two-line format. Execute these sequentially.  Assembler will put them in the proper containers.

ld2w    r2,@r8+         ->

mac     a0,r0,r7

Two-line format. Execute these sequentially.  Same as above but second instruction will always go into right container.  Since $ has no special meaning, you may use it in symbol names.


Register Names
Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax

Register Names

You can use the predefined symbols r0 through r15 to refer to the D10V registers.  You can also use sp as an alias for r15.  The accumulators are a0 and a1.  There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive.

Register Pairs

r0-r1

r2-r3

r4-r5

r6-r7

r8-r9

r10-r11

r12-r13

r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

c

Carry flag


Addressing Modes
Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax

Addressing Modes

as understands the following addressing modes for the D10V.  Rn in the following refers to any of the numbered registers, but not the control registers.

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the # is optional and ignored)


@WORD Modifier
Node: D10V-Word, Next: , Prev: D10V-Addressing, Up: D10V-Syntax

@WORD Modifier

Any symbol followed by @word will be replaced by the symbol's value shifted right by 2.  This is used in situations such as loading a register with the address of a function (or any other code fragment).  For example, if you want to load a register with the location of the function main then jump to that function, you could do it as follws:

ldi     r2, main@word
jmp     r2


Floating Point
Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent

Floating Point

The D10V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools.


Opcodes
Node: D10V-Opcodes, Next: , Prev: D10V-Float, Up: D10V-Dependent

Opcodes

For detailed information on the D10V machine instruction set, see D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.).  as implements all the standard D10V opcodes.  The only changes are those described in the section on size modifiers


H8/300 Dependent Features
Node: H8/300-Dependent, Next: H8/500-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies

H8/300 Dependent Features

* Menu:

H8/300 Options	Options

H8/300 Syntax	Syntax

H8/300 Floating Point	Floating Point

H8/300 Directives	H8/300 Machine Directives

H8/300 Opcodes	Opcodes


Options
Node: H8/300 Options, Next: H8/300 Syntax, Prev: , Up: H8/300-Dependent

Options

as has no additional command-line options for the Hitachi H8/300 family.


Syntax
Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent

Syntax

* Menu:

H8/300-Chars	Special Characters

H8/300-Regs	Register Names

H8/300-Addressing	Addressing Modes


Special Characters
Node: H8/300-Chars, Next: H8/300-Regs, Prev: , Up: H8/300 Syntax

Special Characters

; is the line comment character.

$ can be used instead of a newline to separate statements.  Therefore you may not use $ in symbol names on the H8/300.


Register Names
Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax

Register Names

You can use predefined symbols of the form rnh and rnl to refer to the H8/300 registers as sixteen 8-bit general-purpose registers.  n is a digit from 0 to 7); for instance, both r0h and r7l are valid register names.

You can also use the eight predefined symbols rn to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols ern (er0 ... er7) to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register).  r7 is used as the stack pointer, and can also be called sp.


Addressing Modes
Node: H8/300-Addressing, Next: , Prev: H8/300-Regs, Up: H8/300 Syntax

Addressing Modes

as understands the following addressing modes for the H8/300:

rn

Register direct

@rn

Register indirect

@(d, rn)

@(d:16, rn)

@(d:24, rn)

Register indirect: 16-bit or 24-bit displacement d from register n.  (24-bit displacements are only meaningful on the H8/300H.)

@rn+

Register indirect with post-increment

@-rn

Register indirect with pre-decrement

@aa

@aa:8

@aa:16

@aa:24

Absolute address aa.  (The address size :24 only makes sense on the H8/300H.)

#xx

#xx:8

#xx:16

#xx:32

Immediate data xx.  You may specify the :8, :16, or :32 for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.

@@aa

@@aa:8

Memory indirect.  You may specify the :8 for clarity, if you wish; but as neither requires this nor uses it.


Floating Point
Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent

Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.


H8/300 Machine Directives
Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent

H8/300 Machine Directives

as has only one machine-dependent directive for the H8/300:

.h8300h

Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) .word directives generate 16-bit numbers.


Opcodes
Node: H8/300 Opcodes, Next: , Prev: H8/300 Directives, Up: H8/300-Dependent

Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE-602-025).  For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).

{No Value For "rd{}AS"} implements all the standard H8/300 opcodes.  No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments.  Entries marked * are opcodes used only on the H8/300H.

         Legend:
            Rs   source register
            Rd   destination register
            abs  absolute address
            imm  immediate data
         disp:N  N-bit displacement from a register
        pcrel:N  N-bit displacement relative to program counter

   add.b #imm,rd              *  andc #imm,ccr
   add.b rs,rd                   band #imm,rd
   add.w rs,rd                   band #imm,@rd
*  add.w #imm,rd                 band #imm,@abs:8
*  add.l rs,rd                   bra  pcrel:8
*  add.l #imm,rd              *  bra  pcrel:16
   adds #imm,rd                  bt   pcrel:8
   addx #imm,rd               *  bt   pcrel:16
   addx rs,rd                    brn  pcrel:8
   and.b #imm,rd              *  brn  pcrel:16
   and.b rs,rd                   bf   pcrel:8
*  and.w rs,rd                *  bf   pcrel:16
*  and.w #imm,rd                 bhi  pcrel:8
*  and.l #imm,rd              *  bhi  pcrel:16
*  and.l rs,rd                   bls  pcrel:8

*  bls  pcrel:16                 bld  #imm,rd
   bcc  pcrel:8                  bld  #imm,@rd
*  bcc  pcrel:16                 bld  #imm,@abs:8
   bhs  pcrel:8                  bnot #imm,rd
*  bhs  pcrel:16                 bnot #imm,@rd
   bcs  pcrel:8                  bnot #imm,@abs:8
*  bcs  pcrel:16                 bnot rs,rd
   blo  pcrel:8                  bnot rs,@rd
*  blo  pcrel:16                 bnot rs,@abs:8
   bne  pcrel:8                  bor  #imm,rd
*  bne  pcrel:16                 bor  #imm,@rd
   beq  pcrel:8                  bor  #imm,@abs:8
*  beq  pcrel:16                 bset #imm,rd
   bvc  pcrel:8                  bset #imm,@rd
*  bvc  pcrel:16                 bset #imm,@abs:8
   bvs  pcrel:8                  bset rs,rd
*  bvs  pcrel:16                 bset rs,@rd
   bpl  pcrel:8                  bset rs,@abs:8
*  bpl  pcrel:16                 bsr  pcrel:8
   bmi  pcrel:8                  bsr  pcrel:16
*  bmi  pcrel:16                 bst  #imm,rd
   bge  pcrel:8                  bst  #imm,@rd
*  bge  pcrel:16                 bst  #imm,@abs:8
   blt  pcrel:8                  btst #imm,rd
*  blt  pcrel:16                 btst #imm,@rd
   bgt  pcrel:8                  btst #imm,@abs:8
*  bgt  pcrel:16                 btst rs,rd
   ble  pcrel:8                  btst rs,@rd
*  ble  pcrel:16                 btst rs,@abs:8
   bclr #imm,rd                  bxor #imm,rd
   bclr #imm,@rd                 bxor #imm,@rd
   bclr #imm,@abs:8              bxor #imm,@abs:8
   bclr rs,rd                    cmp.b #imm,rd
   bclr rs,@rd                   cmp.b rs,rd
   bclr rs,@abs:8                cmp.w rs,rd
   biand #imm,rd                 cmp.w rs,rd
   biand #imm,@rd             *  cmp.w #imm,rd
   biand #imm,@abs:8          *  cmp.l #imm,rd
   bild #imm,rd               *  cmp.l rs,rd
   bild #imm,@rd                 daa  rs
   bild #imm,@abs:8              das  rs
   bior #imm,rd                  dec.b rs
   bior #imm,@rd              *  dec.w #imm,rd
   bior #imm,@abs:8           *  dec.l #imm,rd
   bist #imm,rd                  divxu.b rs,rd
   bist #imm,@rd              *  divxu.w rs,rd
   bist #imm,@abs:8           *  divxs.b rs,rd
   bixor #imm,rd              *  divxs.w rs,rd
   bixor #imm,@rd                eepmov
   bixor #imm,@abs:8          *  eepmovw

*  exts.w rd                     mov.w rs,@abs:16
*  exts.l rd                  *  mov.l #imm,rd
*  extu.w rd                  *  mov.l rs,rd
*  extu.l rd                  *  mov.l @rs,rd
   inc  rs                    *  mov.l @(disp:16,rs),rd
*  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
*  inc.l #imm,rd              *  mov.l @rs+,rd
   jmp  @rs                   *  mov.l @abs:16,rd
   jmp  abs                   *  mov.l @abs:24,rd
   jmp  @@abs:8               *  mov.l rs,@rd
   jsr  @rs                   *  mov.l rs,@(disp:16,rd)
   jsr  abs                   *  mov.l rs,@(disp:24,rd)
   jsr  @@abs:8               *  mov.l rs,@-rd
   ldc  #imm,ccr              *  mov.l rs,@abs:16
   ldc  rs,ccr                *  mov.l rs,@abs:24
*  ldc  @abs:16,ccr              movfpe @abs:16,rd
*  ldc  @abs:24,ccr              movtpe rs,@abs:16
*  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
*  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
*  ldc  @rs+,ccr              *  mulxs.b rs,rd
*  ldc  @rs,ccr               *  mulxs.w rs,rd
*  mov.b @(disp:24,rs),rd        neg.b rs
*  mov.b rs,@(disp:24,rd)     *  neg.w rs
   mov.b @abs:16,rd           *  neg.l rs
   mov.b rs,rd                   nop
   mov.b @abs:8,rd               not.b rs
   mov.b rs,@abs:8            *  not.w rs
   mov.b rs,rd                *  not.l rs
   mov.b #imm,rd                 or.b #imm,rd
   mov.b @rs,rd                  or.b rs,rd
   mov.b @(disp:16,rs),rd     *  or.w #imm,rd
   mov.b @rs+,rd              *  or.w rs,rd
   mov.b @abs:8,rd            *  or.l #imm,rd
   mov.b rs,@rd               *  or.l rs,rd
   mov.b rs,@(disp:16,rd)        orc  #imm,ccr
   mov.b rs,@-rd                 pop.w rs
   mov.b rs,@abs:8            *  pop.l rs
   mov.w rs,@rd                  push.w rs
*  mov.w @(disp:24,rs),rd     *  push.l rs
*  mov.w rs,@(disp:24,rd)        rotl.b rs
*  mov.w @abs:24,rd           *  rotl.w rs
*  mov.w rs,@abs:24           *  rotl.l rs
   mov.w rs,rd                   rotr.b rs
   mov.w #imm,rd              *  rotr.w rs
   mov.w @rs,rd               *  rotr.l rs
   mov.w @(disp:16,rs),rd        rotxl.b rs
   mov.w @rs+,rd              *  rotxl.w rs
   mov.w @abs:16,rd           *  rotxl.l rs
   mov.w rs,@(disp:16,rd)        rotxr.b rs
   mov.w rs,@-rd              *  rotxr.w rs

*  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
   bpt                        *  stc  ccr,@-rd
   rte                        *  stc  ccr,@abs:16
   rts                        *  stc  ccr,@abs:24
   shal.b rs                     sub.b rs,rd
*  shal.w rs                     sub.w rs,rd
*  shal.l rs                  *  sub.w #imm,rd
   shar.b rs                  *  sub.l rs,rd
*  shar.w rs                  *  sub.l #imm,rd
*  shar.l rs                     subs #imm,rd
   shll.b rs                     subx #imm,rd
*  shll.w rs                     subx rs,rd
*  shll.l rs                  *  trapa #imm
   shlr.b rs                     xor  #imm,rd
*  shlr.w rs                     xor  rs,rd
*  shlr.l rs                  *  xor.w #imm,rd
   sleep                      *  xor.w rs,rd
   stc  ccr,rd                *  xor.l #imm,rd
*  stc  ccr,@rs               *  xor.l rs,rd
*  stc  ccr,@(disp:16,rd)        xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes .b, .w, and .l to specify the size of a memory operand.  as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register,

mov    r0,@foo

is equivalent to

mov.w  r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.


H8/500 Dependent Features
Node: H8/500-Dependent, Next: HPPA-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies

H8/500 Dependent Features

* Menu:

H8/500 Options	Options

H8/500 Syntax	Syntax

H8/500 Floating Point	Floating Point

H8/500 Directives	H8/500 Machine Directives

H8/500 Opcodes	Opcodes


Options
Node: H8/500 Options, Next: H8/500 Syntax, Prev: , Up: H8/500-Dependent

Options

as has no additional command-line options for the Hitachi H8/500 family.


Syntax
Node: H8/500 Syntax, Next: H8/500 Floating Point, Prev: H8/500 Options, Up: H8/500-Dependent

Syntax

* Menu:

H8/500-Chars	Special Characters

H8/500-Regs	Register Names

H8/500-Addressing	Addressing Modes


Special Characters
Node: H8/500-Chars, Next: H8/500-Regs, Prev: , Up: H8/500 Syntax

Special Characters

! is the line comment character.

; can be used instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.


Register Names
Node: H8/500-Regs, Next: H8/500-Addressing, Prev: H8/500-Chars, Up: H8/500 Syntax

Register Names

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, and r7 to refer to the H8/500 registers.

The H8/500 also has these control registers:

cp

code pointer

dp

data pointer

bp

base pointer

tp

stack top pointer

ep

extra pointer

sr

status register

ccr

condition code register

All registers are 16 bits long.  To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (cp for the program counter; dp for r0-r3; ep for r4 and r5; and tp for r6 and r7.


Addressing Modes
Node: H8/500-Addressing, Next: , Prev: H8/500-Regs, Up: H8/500 Syntax

Addressing Modes

as understands the following addressing modes for the H8/500:

Rn

Register direct

@Rn

Register indirect

@(d:8, Rn)

Register indirect with 8 bit signed displacement

@(d:16, Rn)

Register indirect with 16 bit signed displacement

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@aa:8

8 bit absolute address

@aa:16

16 bit absolute address

#xx:8

8 bit immediate

#xx:16

16 bit immediate


Floating Point
Node: H8/500 Floating Point, Next: H8/500 Directives, Prev: H8/500 Syntax, Up: H8/500-Dependent

Floating Point

The H8/500 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.


H8/500 Machine Directives
Node: H8/500 Directives, Next: H8/500 Opcodes, Prev: H8/500 Floating Point, Up: H8/500-Dependent

H8/500 Machine Directives

as has no machine-dependent directives for the H8/500.  However, on this platform the .int and .word directives generate 16-bit numbers.


Opcodes
Node: H8/500 Opcodes, Next: , Prev: H8/500 Directives, Up: H8/500-Dependent

Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).

{No Value For "rd{}AS"} implements all the standard H8/500 opcodes.  No additional pseudo-instructions are needed on this family.

The following table summarizes H8/500 opcodes and their operands:

Legend:
abs8      8-bit absolute address
abs16     16-bit absolute address
abs24     24-bit absolute address
crb       ccr, br, ep, dp, tp, dp
disp8     8-bit displacement
ea        rn, @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16,
          #xx:8, #xx:16
ea_mem    @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16
ea_noimm  rn, @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16
fp        r6
imm4      4-bit immediate data
imm8      8-bit immediate data
imm16     16-bit immediate data
pcrel8    8-bit offset from program counter
pcrel16   16-bit offset from program counter
qim       -2, -1, 1, 2
rd        any register
rs        a register distinct from rd
rlist     comma-separated list of registers in parentheses;
          register ranges rd-rs are allowed
sp        stack pointer (r7)
sr        status register
sz        size; .b or .w.  If omitted, default .w

ldc[.b] ea,crb                 bcc[.w] pcrel16
ldc[.w] ea,sr                  bcc[.b] pcrel8
add[:q] sz qim,ea_noimm        bhs[.w] pcrel16
add[:g] sz ea,rd               bhs[.b] pcrel8
adds sz ea,rd                  bcs[.w] pcrel16
addx sz ea,rd                  bcs[.b] pcrel8
and sz ea,rd                   blo[.w] pcrel16
andc[.b] imm8,crb              blo[.b] pcrel8
andc[.w] imm16,sr              bne[.w] pcrel16
bpt                            bne[.b] pcrel8
bra[.w] pcrel16                beq[.w] pcrel16
bra[.b] pcrel8                 beq[.b] pcrel8
bt[.w] pcrel16                 bvc[.w] pcrel16
bt[.b] pcrel8                  bvc[.b] pcrel8
brn[.w] pcrel16                bvs[.w] pcrel16
brn[.b] pcrel8                 bvs[.b] pcrel8
bf[.w] pcrel16                 bpl[.w] pcrel16
bf[.b] pcrel8                  bpl[.b] pcrel8
bhi[.w] pcrel16                bmi[.w] pcrel16
bhi[.b] pcrel8                 bmi[.b] pcrel8
bls[.w] pcrel16                bge[.w] pcrel16
bls[.b] pcrel8                 bge[.b] pcrel8

blt[.w] pcrel16                mov[:g][.b] imm8,ea_mem
blt[.b] pcrel8                 mov[:g][.w] imm16,ea_mem
bgt[.w] pcrel16                movfpe[.b] ea,rd
bgt[.b] pcrel8                 movtpe[.b] rs,ea_noimm
ble[.w] pcrel16                mulxu sz ea,rd
ble[.b] pcrel8                 neg sz ea
bclr sz imm4,ea_noimm          nop
bclr sz rs,ea_noimm            not sz ea
bnot sz imm4,ea_noimm          or sz ea,rd
bnot sz rs,ea_noimm            orc[.b] imm8,crb
bset sz imm4,ea_noimm          orc[.w] imm16,sr
bset sz rs,ea_noimm            pjmp abs24
bsr[.b] pcrel8                 pjmp @rd
bsr[.w] pcrel16                pjsr abs24
btst sz imm4,ea_noimm          pjsr @rd
btst sz rs,ea_noimm            prtd imm8
clr sz ea                      prtd imm16
cmp[:e][.b] imm8,rd            prts
cmp[:i][.w] imm16,rd           rotl sz ea
cmp[:g].b imm8,ea_noimm        rotr sz ea
cmp[:g][.w] imm16,ea_noimm     rotxl sz ea
Cmp[:g] sz ea,rd               rotxr sz ea
dadd rs,rd                     rtd imm8
divxu sz ea,rd                 rtd imm16
dsub rs,rd                     rts
exts[.b] rd                    scb/f rs,pcrel8
extu[.b] rd                    scb/ne rs,pcrel8
jmp @rd                        scb/eq rs,pcrel8
jmp @(imm8,rd)                 shal sz ea
jmp @(imm16,rd)                shar sz ea
jmp abs16                      shll sz ea
jsr @rd                        shlr sz ea
jsr @(imm8,rd)                 sleep
jsr @(imm16,rd)                stc[.b] crb,ea_noimm
jsr abs16                      stc[.w] sr,ea_noimm
ldm @sp+,(rlist)               stm (rlist),@-sp
link fp,imm8                   sub sz ea,rd
link fp,imm16                  subs sz ea,rd
mov[:e][.b] imm8,rd            subx sz ea,rd
mov[:i][.w] imm16,rd           swap[.b] rd
mov[:l][.w] abs8,rd            tas[.b] ea
mov[:l].b abs8,rd              trapa imm4
mov[:s][.w] rs,abs8            trap/vs
mov[:s].b rs,abs8              tst sz ea
mov[:f][.w] @(disp8,fp),rd     unlk fp
mov[:f][.w] rs,@(disp8,fp)     xch[.w] rs,rd
mov[:f].b @(disp8,fp),rd       xor sz ea,rd
mov[:f].b rs,@(disp8,fp)       xorc.b imm8,crb
mov[:g] sz rs,ea_mem           xorc.w imm16,sr
mov[:g] sz ea,rd


HPPA Dependent Features
Node: HPPA-Dependent, Next: i386-Dependent, Prev: H8/500-Dependent, Up: Machine Dependencies

HPPA Dependent Features

* Menu:

HPPA Notes	Notes

HPPA Options	Options

HPPA Syntax	Syntax

HPPA Floating Point	Floating Point

HPPA Directives	HPPA Machine Directives

HPPA Opcodes	Opcodes


Notes
Node: HPPA Notes, Next: HPPA Options, Prev: , Up: HPPA-Dependent

Notes

As a back end for GNU CC as has been throughly tested and should work extremely well.  We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers.

The format of the debugging sections has changed since the original as port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats.  Additional relocation support will be added as it becomes necessary.


Options
Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent

Options

{No Value For "rd{}AS"} has no machine-dependent command-line options for the HPPA.


Syntax
Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent

Syntax

The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.

First, a colon may immediately follow a label definition.  This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the spop instructions, or code which makes significant use of the ! line separator.

{No Value For "rd{}AS"} is much less forgiving about missing arguments and other similar oversights than the HP assembler.  as notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, as allows you to use an external symbol without explicitly importing the symbol.  Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

; is the line comment character.

! can be used instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.


Floating Point
Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent

Floating Point

The HPPA family uses IEEE floating-point numbers.


HPPA Assembler Directives
Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent

HPPA Assembler Directives

{No Value For "rd{}AS"} for the HPPA supports many additional directives for compatibility with the native assembler.  This section describes them only briefly.  For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

as does not support the following assembler directives described in the HP manual:

.endm           .liston
.enter          .locct
.leave          .macro
.listoff

Beyond those implemented for compatibility, as supports one additional assembler directive for the HPPA: .param.  It conveys register argument locations for static functions.  Its syntax closely follows the .export directive.

These are the additional directives in as for the HPPA:

.block n

.blockz n

Reserve n bytes of storage, and initialize them to zero.

.call

Mark the beginning of a procedure call.  Only the special case with no arguments is allowed.

.callinfo [ param=value, ... ]  [ flag, ... ]

Specify a number of parameters and flags that define the environment for a procedure.

param may be any of frame (frame size), entry_gr (end of general register range), entry_fr (end of float register range), entry_sr (end of space register range).

The values for flag are calls or caller (proc has subroutines), no_calls (proc does not call subroutines), save_rp (preserve return pointer), save_sp (proc preserves stack pointer), no_unwind (do not unwind this proc), hpux_int (proc is interrupt routine).

.code

Assemble into the standard section called $TEXT$, subsection $CODE$.

.copyright "string"

In the SOM object format, insert string into the object code, marked as a copyright string.

.copyright "string"

In the ELF object format, insert string into the object code, marked as a version string.

.enter

Not yet supported; the assembler rejects programs containing this directive.

.entry

Mark the beginning of a procedure.

.exit

Mark the end of a procedure.

.export name [ ,typ ]  [ ,param=r ]

Make a procedure name available to callers.  typ, if present, must be one of absolute, code (ELF only, not SOM), data, entry, data, entry, millicode, plabel, pri_prog, or sec_prog.

param, if present, provides either relocation information for the procedure arguments and result, or a privilege level.  param may be argwn (where n ranges from 0 to 3, and indicates one of four one-word arguments); rtnval (the procedure's result); or priv_lev (privilege level).  For arguments or the result, r specifies how to relocate, and must be one of no (not relocatable), gr (argument is in general register), fr (in floating point register), or fu (upper half of float register).  For priv_lev, r is an integer.

.half n

Define a two-byte integer constant n; synonym for the portable as directive .short.

.import name [ ,typ ]

Converse of .export; make a procedure available to call.  The arguments use the same conventions as the first two arguments for .export.

.label name

Define name as a label for the current assembly location.

.leave

Not yet supported; the assembler rejects programs containing this directive.

.origin lc

Advance location counter to lc. Synonym for the {No Value For "as"} portable directive .org.

.param name [ ,typ ]  [ ,param=r ]

Similar to .export, but used for static procedures.

.proc

Use preceding the first statement of a procedure.

.procend

Use following the last statement of a procedure.

label .reg expr

Synonym for .equ; define label with the absolute expression expr as its value.

.space secname [ ,params ]

Switch to section secname, creating a new section by that name if necessary.  You may only use params when creating a new section, not when switching to an existing one.  secname may identify a section by number rather than by name.

If specified, the list params declares attributes of the section, identified by keywords.  The keywords recognized are spnum=exp (identify this section by the number exp, an absolute expression), sort=exp (order sections according to this sort key when linking; exp is an absolute expression), unloadable (section contains no loadable data), notdefined (this section defined elsewhere), and private (data in this section not available to other programs).

.spnum secnam

Allocate four bytes of storage, and initialize them with the section number of the section named secnam.  (You can define the section number with the HPPA .space directive.)

.string "str"

Copy the characters in the string str to the object file.  See Strings, for information on escape sequences you can use in as strings.

Warning! The HPPA version of .string differs from the usual as definition: it does not write a zero byte after copying str.

.stringz "str"

Like .string, but appends a zero byte after copying str to object file.

.subspa name [ ,params ]

.nsubspa name [ ,params ]

Similar to .space, but selects a subsection name within the current section.  You may only specify params when you create a subsection (in the first instance of .subspa for this name).

If specified, the list params declares attributes of the subsection, identified by keywords.  The keywords recognized are quad=expr ("quadrant" for this subsection), align=expr (alignment for beginning of this subsection; a power of two), access=expr (value for "access rights" field), sort=expr (sorting order for this subspace in link), code_only (subsection contains only code), unloadable (subsection cannot be loaded into memory), common (subsection is common block), dup_comm (initialized data may have duplicate names), or zero (subsection is all zeros, do not write in object file).

.nsubspa always creates a new subspace with the given name, even if one with the same name already exists.

.version "str"

Write str as version identifier in object code.


Opcodes
Node: HPPA Opcodes, Next: , Prev: HPPA Directives, Up: HPPA-Dependent

Opcodes

For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).


80386 Dependent Features
Node: i386-Dependent, Next: i960-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies

80386 Dependent Features

* Menu:

i386-Options	Options

i386-Syntax	AT&T Syntax versus Intel Syntax

i386-Opcodes	Opcode Naming

i386-Regs	Register Naming

i386-prefixes	Opcode Prefixes

i386-Memory	Memory References

i386-jumps	Handling of Jump Instructions

i386-Float	Floating Point

i386-16bit	Writing 16-bit Code

i386-Notes	Notes


Options
Node: i386-Options, Next: i386-Syntax, Prev: , Up: i386-Dependent

Options

The 80386 has no machine dependent options.


AT&T Syntax versus Intel Syntax
Node: i386-Syntax, Next: i386-Opcodes, Prev: i386-Options, Up: i386-Dependent

AT&T Syntax versus Intel Syntax

In order to maintain compatibility with the output of gcc, as supports AT&T System V/386 assembler syntax.  This is quite different from Intel syntax.  We mention these differences because almost all 80386 documents used only Intel syntax.  Notable differences between the two syntaxes are:

•	AT&T immediate operands are preceded by $; Intel immediate operands are undelimited (Intel push 4 is AT&T pushl $4).  AT&T register operands are preceded by %; Intel register operands are undelimited.  AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by *; they are undelimited in Intel syntax.

•	AT&T and Intel syntax use the opposite order for source and destination operands.  Intel add eax, 4 is addl $4, %eax.  The source, dest convention is maintained for compatibility with previous Unix assemblers.

•	In AT&T syntax the size of memory operands is determined from the last character of the opcode name.  Opcode suffixes of b, w, and l specify byte (8-bit), word (16-bit), and long (32-bit) memory references.  Intel syntax accomplishes this by prefixes memory operands (not the opcodes themselves) with byte ptr, word ptr, and dword ptr.  Thus, Intel mov al, byte ptr foo is movb foo, %al in AT&T syntax.

•	Immediate form long jumps and calls are lcall/ljmp $section, $offset in AT&T syntax; the Intel syntax is call/jmp far section:offset.  Also, the far return instruction is lret $stack-adjust in AT&T syntax; Intel syntax is ret far stack-adjust.

•	The AT&T assembler does not provide support for multiple section programs.  Unix style systems expect all programs to be single sections.


Opcode Naming
Node: i386-Opcodes, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent

Opcode Naming

Opcode names are suffixed with one character modifiers which specify the size of operands.  The letters b, w, and l specify byte, word, and long operands.  If no suffix is specified by an instruction and it contains no memory operands then as tries to fill in the missing suffix based on the destination register operand (the last one by convention).  Thus, mov %ax, %bx is equivalent to movw %ax, %bx; also, mov $1, %bx is equivalent to movw $1, %bx.  Note that this is incompatible with the AT&T Unix assembler which assumes that a missing opcode suffix implies long operand size.  (This incompatibility does not affect compiler output since compilers always explicitly specify the opcode suffix.)

Almost all opcodes have the same names in AT&T and Intel format.  There are a few exceptions.  The sign extend and zero extend instructions need two sizes to specify them.  They need a size to sign/zero extend from and a size to zero extend to.  This is accomplished by using two opcode suffixes in AT&T syntax.  Base names for sign extend and zero extend are movs... and movz... in AT&T syntax (movsx and movzx in Intel syntax).  The opcode suffixes are tacked on to this base name, the from suffix before the to suffix.  Thus, movsbl %al, %edx is AT&T syntax for "move sign extend from %al to %edx."  Possible suffixes, thus, are bl (from byte to long), bw (from byte to word), and wl (from word to long).

The Intel-syntax conversion instructions

•	cbw -- sign-extend byte in %al to word in %ax,

•	cwde -- sign-extend word in %ax to long in %eax,

•	cwd -- sign-extend word in %ax to long in %dx:%ax,

•	cdq -- sign-extend dword in %eax to quad in %edx:%eax,

are called cbtw, cwtl, cwtd, and cltd in AT&T naming.  as accepts either naming for these instructions.

Far call/jump instructions are lcall and ljmp in AT&T syntax, but are call far and jump far in Intel convention.


Register Naming
Node: i386-Regs, Next: i386-prefixes, Prev: i386-Opcodes, Up: i386-Dependent

Register Naming

Register operands are always prefixes with %.  The 80386 registers consist of

•	the 8 32-bit registers %eax (the accumulator), %ebx, %ecx, %edx, %edi, %esi, %ebp (the frame pointer), and %esp (the stack pointer).

•	the 8 16-bit low-ends of these: %ax, %bx, %cx, %dx, %di, %si, %bp, and %sp.

•	the 8 8-bit registers: %ah, %al, %bh, %bl, %ch, %cl, %dh, and %dl (These are the high-bytes and low-bytes of %ax, %bx, %cx, and %dx)

•	the 6 section registers %cs (code section), %ds (data section), %ss (stack section), %es, %fs, and %gs.

•	the 3 processor control registers %cr0, %cr2, and %cr3.

•	the 6 debug registers %db0, %db1, %db2, %db3, %db6, and %db7.

•	the 2 test registers %tr6 and %tr7.

•	the 8 floating point register stack %st or equivalently %st(0), %st(1), %st(2), %st(3), %st(4), %st(5), %st(6), and %st(7).


Opcode Prefixes
Node: i386-prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent

Opcode Prefixes

Opcode prefixes are used to modify the following opcode.  They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to give operand and address size (16-bit operands are specified in an instruction by prefixing what would normally be 32-bit operands with a "operand size" opcode prefix).  Opcode prefixes are usually given as single-line instructions with no operands, and must directly precede the instruction they act upon.  For example, the scas (scan string) instruction is repeated with:

        repne
        scas

Here is a list of opcode prefixes:

•	Section override prefixes cs, ds, ss, es, fs, gs.  These are automatically added by specifying using the section:memory-operand form for memory references.

•	Operand/Address size prefixes data16 and addr16 change 32-bit operands/addresses into 16-bit operands/addresses.  Note that 16-bit addressing modes (i.e. 8086 and 80286 addressing modes) are not supported (yet).

•	The bus lock prefix lock inhibits interrupts during execution of the instruction it precedes.  (This is only valid with certain instructions; see a 80386 manual for details).

•	The wait for coprocessor prefix wait waits for the coprocessor to complete the current instruction.  This should never be needed for the 80386/80387 combination.

•	The rep, repe, and repne prefixes are added to string instructions to make them repeat %ecx times.


Memory References
Node: i386-Memory, Next: i386-jumps, Prev: i386-prefixes, Up: i386-Dependent

Memory References

An Intel syntax indirect memory reference of the form

section:[base + index*scale + disp]

is translated into the AT&T syntax

section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand.  If no scale is specified, scale is taken to be 1.  section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must have be preceded by a %.  If you specify a section override which coincides with the default section register, as does not output any section register override prefixes to assemble the given instruction.  Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: -4(%ebp), Intel:  [ebp - 4]

base is %ebp; disp is -4. section is missing, and the default section is used (%ss for addressing with %ebp as the base register).  index, scale are both missing.

AT&T: foo(,%eax,4), Intel: [foo + eax*4]

index is %eax (scaled by a scale 4); disp is foo.  All other fields are missing.  The section register here defaults to %ds.

AT&T: foo(,1); Intel [foo]

This uses the value pointed to by foo as a memory operand.  Note that base and index are both missing, but there is only one ,.  This is a syntactic exception.

AT&T: %gs:foo; Intel gs:foo

This selects the contents of the variable foo with section register section being %gs.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with *.  If no * is specified, as always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand must specify its size (byte, word, or long) with an opcode suffix (b, w, or l, respectively).


Handling of Jump Instructions
Node: i386-jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent

Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements.  This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close.  If a byte displacement is insufficient a long (32-bit) displacement is used.  We do not support word (16-bit) displacement jumps (i.e. prefixing the jump instruction with the addr16 opcode prefix), since the 80386 insists upon masking %eip to 16 bits after the word displacement is added.

Note that the jcxz, jecxz, loop, loopz, loope, loopnz and loopne instructions only come in byte displacements, so that if you use these instructions (gcc does not use them) you may get an error message (and incorrect code).  The AT&T 80386 assembler tries to get around this problem by expanding jcxz foo to

         jcxz cx_zero
         jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:


Floating Point
Node: i386-Float, Next: i386-16bit, Prev: i386-jumps, Up: i386-Dependent

Floating Point

All 80387 floating point types except packed BCD are supported.  (BCD support may be added without much difficulty).  These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point.  Each supported type has an opcode suffix and a constructor associated with it.  Opcode suffixes specify operand's data types.  Constructors build these data types into memory.

•	Floating point constructors are .float or .single, .double, and .tfloat for 32-, 64-, and 80-bit formats.  These correspond to opcode suffixes s, l, and t.  t stands for temporary real, and that the 80387 only supports this format via the fldt (load temporary real to stack top) and fstpt (store temporary real and pop stack) instructions.

•	Integer constructors are .word, .long or .int, and .quad for the 16-, 32-, and 64-bit integer formats.  The corresponding opcode suffixes are s (single), l (long), and q (quad).  As with the temporary real format the 64-bit q format is only present in the fildq (load quad integer to stack top) and fistpq (store quad integer and pop stack) instructions.

Register to register operations do not require opcode suffixes, so that fst %st, %st(1) is equivalent to fstl %st, %st(1).


Writing 16-bit Code
Node: i386-16bit, Next: i386-Notes, Prev: i386-Float, Up: i386-Dependent

Writing 16-bit Code

While GAS normally writes only "pure" 32-bit i386 code, it has limited support for writing code to run in real mode or in 16-bit protected mode code segments.  To do this, insert a .code16 directive before the assembly language instructions to be run in 16-bit mode.  You can switch GAS back to writing normal 32-bit code with the .code32 directive.

GAS understands exactly the same assembly language syntax in 16-bit mode as in 32-bit mode.  The function of any given instruction is exactly the same regardless of mode, as long as the resulting object code is executed in the mode for which GAS wrote it.  So, for example, the ret mnemonic produces a 32-bit return instruction regardless of whether it is to be run in 16-bit or 32-bit mode.  (If GAS is in 16-bit mode, it will add an operand size prefix to the instruction to force it to be a 32-bit return.)

This means, for one thing, that you can use GNU CC to write code to be run in real mode or 16-bit protected mode.  Just insert the statement asm(".code16"); at the beginning of your C source file, and while GNU CC will still be generating 32-bit code, GAS will automatically add all the necessary size prefixes to make that code run in 16-bit mode.  Of course, since GNU CC only writes small-model code (it doesn't know how to attach segment selectors to pointers like native x86 compilers do), any 16-bit code you write with GNU CC will essentially be limited to a 64K address space.  Also, there will be a code size and performance penalty due to all the extra address and operand size prefixes GAS has to add to the instructions.

Note that placing GAS in 16-bit mode does not mean that the resulting code will necessarily run on a 16-bit pre-80386 processor.  To write code that runs on such a processor, you would have to refrain from using any 32-bit constructs which require GAS to output address or operand size prefixes.  At the moment this would be rather difficult, because GAS currently supports only 32-bit addressing modes: when writing 16-bit code, it always outputs address size prefixes for any instruction that uses a non-register addressing mode.  So you can write code that runs on 16-bit processors, but only if that code never references memory.


Notes
Node: i386-Notes, Next: , Prev: i386-16bit, Up: i386-Dependent

Notes

There is some trickery concerning the mul and imul instructions that deserves mention.  The 16-, 32-, and 64-bit expanding multiplies (base opcode 0xf6; extension 4 for mul and 5 for imul) can be output only in the one operand form.  Thus, imul %ebx, %eax does not select the expanding multiply; the expanding multiply would clobber the %edx register, and this would confuse gcc output.  Use imul %ebx to get the 64-bit product in %edx:%eax.

We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register.  This is just a shorthand, so that, multiplying %eax by 69, for example, can be done with imul $69, %eax rather than imul $69, %eax, %eax.


Intel 80960 Dependent Features
Node: i960-Dependent, Next: M32R-Dependent, Prev: i386-Dependent, Up: Machine Dependencies

Intel 80960 Dependent Features

* Menu:

Options-i960	i960 Command-line Options

Floating Point-i960	Floating Point

Directives-i960	i960 Machine Directives

Opcodes for i960	i960 Opcodes


i960 Command-line Options
Node: Options-i960, Next: Floating Point-i960, Prev: , Up: i960-Dependent

i960 Command-line Options

-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC

Select the 80960 architecture.  Instructions or features not supported by the selected architecture cause fatal errors.

-ACA is equivalent to -ACA_A; -AKC is equivalent to -AMC.  Synonyms are provided for compatibility with other tools.

If you do not specify any of these options, as generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!).  In principle, as attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file.  If it is critical that the as output match a specific architecture, specify that architecture explicitly.

-b

Add code to collect information about conditional branches taken, for later optimization using branch prediction bits.  (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.)  If BR represents a conditional branch instruction, the following represents the code generated by the assembler when -b is specified:

        call    increment routine
        .word   0       # pre-counter
Label:  BR
        call    increment routine
        .word   0       # post-counter

The counter following a branch records the number of times that branch was not taken; the differenc between the two counters is the number of times the branch was taken.

A table of every such Label is also generated, so that the external postprocessor gbr960 (supplied by Intel) can locate all the counters.  This table is always labelled __BRANCH_TABLE__; this is a local symbol to permit collecting statistics for many separate object files.  The table is word aligned, and begins with a two-word header.  The first word, initialized to 0, is used in maintaining linked lists of branch tables.  The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above.

 +------------+------------+------------+ ... +------------+
 |            |            |            |     |            |
 |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
 |            |            |            |     |            |
 +------------+------------+------------+ ... +------------+

               __BRANCH_TABLE__ layout

The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file.  The GNU C compiler generates these calls automatically when you give it a -b option.  For further details, see the documentation of gbr960.

-no-relax

Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or chkbit) and branch instructions.  You can use the -no-relax option to specify that as should generate errors instead, if the target displacement is larger than 13 bits.

This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use -no-relax.


Floating Point
Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent

Floating Point

as generates IEEE floating-point numbers for the directives .float, .double, .extended, and .single.


i960 Machine Directives
Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent

i960 Machine Directives

.bss symbol, length, align

Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align.  length and align must be positive absolute expressions.  This directive differs from .lcomm only in that it permits you to specify an alignment.  See .lcomm.

.extended flonums

.extended expects zero or more flonums, separated by commas; for each flonum, .extended emits an IEEE extended-format (80-bit) floating-point number.

.leafproc call-lab, bal-lab

You can use the .leafproc directive in conjunction with the optimized callj instruction to enable faster calls of leaf procedures.  If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using .leafproc.  If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab.

A .leafproc declaration is meant for use in conjunction with the optimized call instruction callj; the directive records the data needed later to choose between converting the callj into a bal or a call.

call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the bal entry point.

.sysproc name, index

The .sysproc directive defines a name for a system procedure.  After you define it using .sysproc, you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction callj.

Both arguments are required; index must be between 0 and 31 (inclusive).


i960 Opcodes
Node: Opcodes for i960, Next: , Prev: Directives-i960, Up: i960-Dependent

i960 Opcodes

All Intel 960 machine instructions are supported; see i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: callj, and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

* Menu:

callj-i960	callj

Compare-and-branch-i960	Compare-and-Branch


callj
Node: callj-i960, Next: Compare-and-branch-i960, Prev: , Up: Opcodes for i960

callj

You can write callj to have the assembler or the linker determine the most appropriate form of subroutine call: call, bal, or calls.  If the assembly source contains enough information--a .leafproc or .sysproc directive defining the operand--then as translates the callj; if not, it simply emits the callj, leaving it for the linker to resolve.


Compare-and-Branch
Node: Compare-and-branch-i960, Next: , Prev: callj-i960, Up: Opcodes for i960

Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself.  However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether as gives an error or expands the instruction depends on two choices you can make: whether you use the -no-relax option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction.  The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify -no-relax--in which case as gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:

        Compare and
     Branch      Jump       Expanded to
     ------    ------       ------------
        bbc                 chkbit; bno
        bbs                 chkbit; bo
     cmpibe    cmpije       cmpi; be
     cmpibg    cmpijg       cmpi; bg
    cmpibge   cmpijge       cmpi; bge
     cmpibl    cmpijl       cmpi; bl
    cmpible   cmpijle       cmpi; ble
    cmpibno   cmpijno       cmpi; bno
    cmpibne   cmpijne       cmpi; bne
     cmpibo    cmpijo       cmpi; bo
     cmpobe    cmpoje       cmpo; be
     cmpobg    cmpojg       cmpo; bg
    cmpobge   cmpojge       cmpo; bge
     cmpobl    cmpojl       cmpo; bl
    cmpoble   cmpojle       cmpo; ble
    cmpobne   cmpojne       cmpo; bne


M32R Dependent Features
Node: M32R-Dependent, Next: M68K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies

M32R Dependent Features

* Menu:

M32R-Opts	M32R Options


M32R Options
Node: M32R-Opts, Next: , Prev: , Up: M32R-Dependent

M32R Options

The Mitsubishi M32R version of as has a few machine dependent options.


M680x0 Dependent Features
Node: M68K-Dependent, Next: MIPS-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies

M680x0 Dependent Features

* Menu:

M68K-Opts	M680x0 Options

M68K-Syntax	Syntax

M68K-Moto-Syntax	Motorola Syntax

M68K-Float	Floating Point

M68K-Directives	680x0 Machine Directives

M68K-opcodes	Opcodes


M680x0 Options
Node: M68K-Opts, Next: M68K-Syntax, Prev: , Up: M68K-Dependent

M680x0 Options

The Motorola 680x0 version of as has a few machine dependent options.

You can use the -l option to shorten the size of references to undefined symbols.  If you do not use the -l option, references to undefined symbols are wide enough for a full long (32 bits).  (Since as cannot know where these symbols end up, as can only allocate space for the linker to fill in later.  Since as does not know how far away these symbols are, it allocates as much space as it can.)  If you use this option, the references are only one word wide (16 bits).  This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a % before any use of a register name.  This is intended to let the assembler distinguish between C variables and functions named a0 through a7, and so on.  The % is always accepted, but is not required for certain configurations, notably sun3.  The --register-prefix-optional option may be used to permit omitting the % even for configurations for which it is normally required.  If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

Normally the character | is treated as a comment character, which means that it can not be used in expressions.  The --bitwise-or option turns | into a normal character.  In this mode, you must either use C style comments, or start comments with a # character at the beginning of a line.

If you use an addressing mode with a base register without specifying the size, as will normally use the full 32 bit value.  For example, the addressing mode %a0@(%d0) is equivalent to %a0@(%d0:l).  You may use the --base-size-default-16 option to tell as to default to using the 16 bit value.  In this case, %a0@(%d0) is equivalent to %a0@(%d0:w).  You may use the --base-size-default-32 option to restore the default behaviour.

If you use an addressing mode with a displacement, and the value of the displacement is not known, as will normally assume that the value is 32 bits.  For example, if the symbol disp has not been defined, as will assemble the addressing mode %a0@(disp,%d0) as though disp is a 32 bit value.  You may use the --disp-size-default-16 option to tell as to instead assume that the displacement is 16 bits.  In this case, as will assemble %a0@(disp,%d0) as though disp is a 16 bit value.  You may use the --disp-size-default-32 option to restore the default behaviour.

as can assemble code for several different members of the Motorola 680x0 family.  The default depends upon how as was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor.  The following options may be used to change the default.  These options control which instructions and addressing modes are permitted.  The members of the 680x0 family are very similar.  For detailed information about the differences, see the Motorola manuals.

-m68000

-m68ec000

-m68hc000

-m68hc001

-m68008

-m68302

-m68306

-m68307

-m68322

-m68356

Assemble for the 68000. -m68008, -m68302, and so on are synonyms for -m68000, since the chips are the same from the point of view of the assembler.

-m68010

Assemble for the 68010.

-m68020

-m68ec020

Assemble for the 68020.  This is normally the default.

-m68030

-m68ec030

Assemble for the 68030.

-m68040

-m68ec040

Assemble for the 68040.

-m68060

-m68ec060

Assemble for the 68060.

-mcpu32

-m68330

-m68331

-m68332

-m68333

-m68334

-m68336

-m68340

-m68341

-m68349

-m68360

Assemble for the CPU32 family of chips.

-m5200

Assemble for the ColdFire family of chips.

-m68881

-m68882

Assemble 68881 floating point instructions.  This is the default for the 68020, 68030, and the CPU32.  The 68040 and 68060 always support floating point instructions.

-mno-68881

Do not assemble 68881 floating point instructions.  This is the default for 68000 and the 68010.  The 68040 and 68060 always support floating point instructions, even if this option is used.

-m68851

Assemble 68851 MMU instructions.  This is the default for the 68020, 68030, and 68060.  The 68040 accepts a somewhat different set of MMU instructions; -m68851 and -m68040 should not be used together.

-mno-68851

Do not assemble 68851 MMU instructions.  This is the default for the 68000, 68010, and the CPU32.  The 68040 accepts a somewhat different set of MMU instructions.


Syntax
Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent

Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler.  Intervening periods are ignored; for example, movl is equivalent to mov.l.

In the following table apc stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), a suppressed address register (%za0 through %za7), or it may be omitted entirely.  The use of size means one of w or l, and it may be omitted, along with the leading colon, unless a scale is also specified.  The use of scale means one of 1, 2, 4, or 8, and it may always be omitted along with the leading colon.

The following addressing modes are understood:

"Immediate"

#number

"Data Register"

%d0 through %d7

"Address Register"

%a0 through %a7

%a7 is also known as %sp, i.e. the Stack Pointer.  %a6 is also known as %fp, the Frame Pointer.

"Address Register Indirect"

%a0@ through %a7@

"Address Register Postincrement"

%a0@+ through %a7@+

"Address Register Predecrement"

%a0@- through %a7@-

"Indirect Plus Offset"

apc@(number)

"Index"

apc@(number,register:size:scale)

The number may be omitted.

"Postindex"

apc@(number)@(onumber,register:size:scale)

The onumber or the register, but not both, may be omitted.

"Preindex"

apc@(number,register:size:scale)@(onumber)

The number may be omitted.  Omitting the register produces the Postindex addressing mode.

"Absolute"

symbol, or digits, optionally followed by :b, :w, or :l.


Motorola Syntax
Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent

Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see Syntax).  as can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction.  The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), or a suppressed address register (%za0 through %za7).  The use of size means one of w or l, and it may always be omitted along with the leading dot.  The use of scale means one of 1, 2, 4, or 8, and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

"Address Register Indirect"

(%a0) through (%a7)

%a7 is also known as %sp, i.e. the Stack Pointer.  %a6 is also known as %fp, the Frame Pointer.

"Address Register Postincrement"

(%a0)+ through (%a7)+

"Address Register Predecrement"

-(%a0) through -(%a7)

"Indirect Plus Offset"

number(%a0) through number(%a7), or number(%pc).

The number may also appear within the parentheses, as in (number,%a0).  When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).

"Index"

number(apc,register.size*scale)

The number may be omitted, or it may appear within the parentheses.  The apc may be omitted.  The register and the apc may appear in either order.  If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

"Postindex"

([number,apc],register.size*scale,onumber)

The onumber, or the register, or both, may be omitted.  Either the number or the apc may be omitted, but not both.

"Preindex"

([number,apc,register.size*scale],onumber)

The number, or the apc, or the register, or any two of them, may be omitted.  The onumber may be omitted.  The register and the apc may appear in either order.  If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.


Floating Point
Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent

Floating Point

Packed decimal (P) format floating literals are not supported.  Feel free to add the code!

The floating point formats generated by directives are these.

.float

Single precision floating point constants.

.double

Double precision floating point constants.

.extend

.ldouble

Extended precision (long double) floating point constants.


680x0 Machine Directives
Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent

680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

.data1

This directive is identical to a .data 1 directive.

.data2

This directive is identical to a .data 2 directive.

.even

This directive is a special case of the .align directive; it aligns the output to an even byte boundary.

.skip

This directive is identical to a .space directive.


Opcodes
Node: M68K-opcodes, Next: , Prev: M68K-Directives, Up: M68K-Dependent

Opcodes

* Menu:

M68K-Branch	Branch Improvement

M68K-Chars	Special Characters


Branch Improvement
Node: M68K-Branch, Next: M68K-Chars, Prev: , Up: M68K-opcodes

Branch Improvement

Certain pseudo opcodes are permitted for branch instructions.  They expand to the shortest branch instruction that reach the target.  Generally these mnemonics are made by substituting j for b at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations.  A * flags cases that are more fully described after the table:

          Displacement
          +-------------------------------------------------
          |                68020   68000/10
Pseudo-Op |BYTE    WORD    LONG    LONG      non-PC relative
          +-------------------------------------------------
     jbsr |bsrs    bsr     bsrl    jsr       jsr
      jra |bras    bra     bral    jmp       jmp
*     jXX |bXXs    bXX     bXXl    bNXs;jmpl bNXs;jmp
*    dbXX |dbXX    dbXX        dbXX; bra; jmpl
*    fjXX |fbXXw   fbXXw   fbXXl             fbNXw;jmp

XX: condition
NX: negative of condition XX

*--see full description below

jbsr

jra

These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

jXX

Here, jXX stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test.  The full list of pseudo-ops in this family is:

 jhi   jls   jcc   jcs   jne   jeq   jvc
 jvs   jpl   jmi   jge   jlt   jgt   jle

For the cases of non-PC relative displacements and long displacements on the 68000 or 68010, as issues a longer code fragment in terms of NX, the opposite condition to XX.  For example, for the non-PC relative case:

    jXX foo

gives

     bNXs oof
     jmp foo
 oof:

dbXX

The full family of pseudo-operations covered here is

 dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
 dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
 dbf    dbra   dbt

Other than for word and byte displacements, when the source reads dbXX foo, as emits

     dbXX oo1
     bra oo2
 oo1:jmpl foo
 oo2:

fjXX

This family includes

 fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
 fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
 fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
 fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
 fjugt  fjule  fjult  fjun

For branch targets that are not PC relative, as emits

     fbNX oof
     jmp foo
 oof:

when it encounters fjXX foo.


Special Characters
Node: M68K-Chars, Next: , Prev: M68K-Branch, Up: M68K-opcodes

Special Characters

The immediate character is # for Sun compatibility.  The line-comment character is | (unless the --bitwise-or option is used).  If a # appears at the beginning of a line, it is treated as a comment unless it looks like # line file, in which case it is treated normally.


MIPS Dependent Features
Node: MIPS-Dependent, Next: SH-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies

MIPS Dependent Features

GNU as for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through IV.  For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).  For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

* Menu:

MIPS Opts	Assembler options

MIPS Object	ECOFF object code

MIPS Stabs	Directives for debugging information

MIPS ISA	Directives to override the ISA level

MIPS autoextend	Directives for extending MIPS 16 bit instructions

MIPS insn	Directive to mark data as an instruction

MIPS option stack	Directives to save and restore options


Assembler options
Node: MIPS Opts, Next: MIPS Object, Prev: , Up: MIPS-Dependent

Assembler options

The MIPS configurations of GNU as support these special options:

-G num

This option sets the largest size of an object that can be referenced implicitly with the gp register.  It is only accepted for targets that use ECOFF format.  The default value is 8.

-EB

-EL

Any MIPS configuration of as can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other).  Use -EB to select big-endian output, and -EL for little-endian.

-mips1

-mips2

-mips3

-mips4

Generate code for a particular MIPS Instruction Set Architecture level.  -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, -mips3 to the R4000 processor, and -mips4 to the R8000 and R10000 processors.  You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mips16

-no-mips16

Generate code for the MIPS 16 processor.  This is equivalent to putting .set mips16 at the start of the assembly file.  -no-mips16 turns off this option.

-m4650

-no-m4650

Generate code for the MIPS R4650 chip.  This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4650 turns off this option.

-m4010

-no-m4010

Generate code for the LSI R4010 chip.  This tells the assembler to accept the R4010 specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4010 turns off this option.

-mcpu=CPU

Generate code for a particular MIPS cpu.  This has little effect on the assembler, but it is passed by gcc.

-nocpp

This option is ignored.  It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing.  With GNU as, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.

--trap

--no-break

{No Value For "\li720{}AS"} automatically macro expands certain division and multiplication instructions to check for overflow and division by zero.  This option causes as to generate code to take a trap exception rather than a break exception when an error is detected.  The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break

--no-trap

Generate code to take a break exception rather than a trap exception when an error is detected.  This is the default.


MIPS ECOFF object code
Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent

MIPS ECOFF object code

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss.  The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a "small object".  Any object in the .sdata or .sbss sections is considered "small" in this sense.  For external objects, or for objects in the .bss section, you can use the gcc -G option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp.  Passing -G 0 to as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case).  The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it.  The size of an external object may be set with the .extern directive.  For example, .extern sym,4 declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code).  MIPS ECOFF assembly code must not modify the $gp register.


Directives for debugging information
Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent

Directives for debugging information

MIPS ECOFF as supports several directives used for generating debugging information which are not support by traditional MIPS assemblers.  These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs.  The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging).  These directives are primarily used by compilers, not assembly language programmers!


Directives to override the ISA level
Node: MIPS ISA, Next: MIPS autoextend, Prev: MIPS Stabs, Up: MIPS-Dependent

Directives to override the ISA level

GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsn.  n should be a number from 0 to 4.  A value from 1 to 4 makes the assembler accept instructions for the corresponding ISA level, from that point on in the assembly.  .set mipsn affects not only which instructions are permitted, but also how certain macros are expanded.  .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration.  You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode.  Use this directive with care!

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor.  Use .set nomips16 to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.


Directives for extending MIPS 16 bit instructions
Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS ISA, Up: MIPS-Dependent

Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary.  The directive .set noautoextend will turn this off.  When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000).  The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode.  Traditional MIPS assemblers do not support this directive.


Directive to mark data as an instruction
Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent

Directive to mark data as an instruction

The .insn directive tells as that the following data is actually instructions.  This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.


Directives to save and restore options
Node: MIPS option stack, Next: , Prev: MIPS insn, Up: MIPS-Dependent

Directives to save and restore options

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set.  The .set push directive saves the current settings on a stack.  The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.


Hitachi SH Dependent Features
Node: SH-Dependent, Next: Sparc-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies

Hitachi SH Dependent Features

* Menu:

SH Options	Options

SH Syntax	Syntax

SH Floating Point	Floating Point

SH Directives	SH Machine Directives

SH Opcodes	Opcodes


Options
Node: SH Options, Next: SH Syntax, Prev: , Up: SH-Dependent

Options

as has no additional command-line options for the Hitachi SH family.


Syntax
Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent

Syntax

* Menu:

SH-Chars	Special Characters

SH-Regs	Register Names

SH-Addressing	Addressing Modes


Special Characters
Node: SH-Chars, Next: SH-Regs, Prev: , Up: SH Syntax

Special Characters

! is the line comment character.

You can use ; instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.


Register Names
Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax

Register Names

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, and r15 to refer to the SH registers.

The SH also has these control registers:

pr

procedure register (holds return address)

pc

program counter

mach

macl

high and low multiply accumulator registers

sr

status register

gbr

global base register

vbr

vector base register (for interrupt vectors)


Addressing Modes
Node: SH-Addressing, Next: , Prev: SH-Regs, Up: SH Syntax

Addressing Modes

as understands the following addressing modes for the SH.  Rn in the following refers to any of the numbered registers, but not the control registers.

Rn

Register direct

@Rn

Register indirect

@-Rn

Register indirect with pre-decrement

@Rn+

Register indirect with post-increment

@(disp, Rn)

Register indirect with displacement

@(R0, Rn)

Register indexed

@(disp, GBR)

GBR offset

@(R0, GBR)

GBR indexed

addr

@(disp, PC)

PC relative address (for branch or for addressing memory).  The as implementation allows you to use the simpler form addr anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.

#imm

Immediate data


Floating Point
Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent

Floating Point

The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.


SH Machine Directives
Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent

SH Machine Directives

uaword

ualong

{No Value For "\li720{}AS"} will issue a warning when a misaligned .word or .long directive is used.  You may use .uaword or .ualong to indicate that the value is intentionally misaligned.


Opcodes
Node: SH Opcodes, Next: , Prev: SH Directives, Up: SH-Dependent

Opcodes

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).

{No Value For "rd{}AS"} implements all the standard SH opcodes.  No additional pseudo-instructions are needed on this family.  Note, however, that because as supports a simpler form of PC-relative addressing, you may simply write (for example)

mov.l  bar,r0

where other assemblers might require an explicit displacement to bar from the program counter:

mov.l  @(disp, PC)

Here is a summary of SH opcodes:

Legend:
Rn        a numbered register
Rm        another numbered register
#imm      immediate data
disp      displacement
disp8     8-bit displacement
disp12    12-bit displacement

add #imm,Rn                    lds.l @Rn+,PR
add Rm,Rn                      mac.w @Rm+,@Rn+
addc Rm,Rn                     mov #imm,Rn
addv Rm,Rn                     mov Rm,Rn
and #imm,R0                    mov.b Rm,@(R0,Rn)
and Rm,Rn                      mov.b Rm,@-Rn
and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
bf disp8                       mov.b @(disp,Rm),R0
bra disp12                     mov.b @(disp,GBR),R0
bsr disp12                     mov.b @(R0,Rm),Rn
bt disp8                       mov.b @Rm+,Rn
clrmac                         mov.b @Rm,Rn
clrt                           mov.b R0,@(disp,Rm)
cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
cmp/gt Rm,Rn                   mov.l Rm,@-Rn
cmp/hi Rm,Rn                   mov.l Rm,@Rn
cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
cmp/pl Rn                      mov.l @(disp,GBR),R0
cmp/pz Rn                      mov.l @(disp,PC),Rn
cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
div0s Rm,Rn                    mov.l @Rm+,Rn
div0u                          mov.l @Rm,Rn
div1 Rm,Rn                     mov.l R0,@(disp,GBR)
exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
exts.w Rm,Rn                   mov.w Rm,@-Rn
extu.b Rm,Rn                   mov.w Rm,@Rn
extu.w Rm,Rn                   mov.w @(disp,Rm),R0
jmp @Rn                        mov.w @(disp,GBR),R0
jsr @Rn                        mov.w @(disp,PC),Rn
ldc Rn,GBR                     mov.w @(R0,Rm),Rn
ldc Rn,SR                      mov.w @Rm+,Rn
ldc Rn,VBR                     mov.w @Rm,Rn
ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
ldc.l @Rn+,VBR                 mova @(disp,PC),R0
lds Rn,MACH                    movt Rn
lds Rn,MACL                    muls Rm,Rn
lds Rn,PR                      mulu Rm,Rn
lds.l @Rn+,MACH                neg Rm,Rn
lds.l @Rn+,MACL                negc Rm,Rn

nop                            stc VBR,Rn
not Rm,Rn                      stc.l GBR,@-Rn
or #imm,R0                     stc.l SR,@-Rn
or Rm,Rn                       stc.l VBR,@-Rn
or.b #imm,@(R0,GBR)            sts MACH,Rn
rotcl Rn                       sts MACL,Rn
rotcr Rn                       sts PR,Rn
rotl Rn                        sts.l MACH,@-Rn
rotr Rn                        sts.l MACL,@-Rn
rte                            sts.l PR,@-Rn
rts                            sub Rm,Rn
sett                           subc Rm,Rn
shal Rn                        subv Rm,Rn
shar Rn                        swap.b Rm,Rn
shll Rn                        swap.w Rm,Rn
shll16 Rn                      tas.b @Rn
shll2 Rn                       trapa #imm
shll8 Rn                       tst #imm,R0
shlr Rn                        tst Rm,Rn
shlr16 Rn                      tst.b #imm,@(R0,GBR)
shlr2 Rn                       xor #imm,R0
shlr8 Rn                       xor Rm,Rn
sleep                          xor.b #imm,@(R0,GBR)
stc GBR,Rn                     xtrct Rm,Rn
stc SR,Rn


SPARC Dependent Features
Node: Sparc-Dependent, Next: V850-Dependent, Prev: SH-Dependent, Up: Machine Dependencies

SPARC Dependent Features

* Menu:

Sparc-Opts	Options

Sparc-Aligned-Data	Option to enforce aligned data

Sparc-Float	Floating Point

Sparc-Directives	Sparc Machine Directives


Options
Node: Sparc-Opts, Next: Sparc-Aligned-Data, Prev: , Up: Sparc-Dependent

Options

The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level.  There are exceptions to this however.  For details on what instructions each variant supports, please see the chip's architecture reference manual.

By default, as assumes the core instruction set (SPARC v6), but "bumps" the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels.

If not configured for SPARC v9 (sparc64-*-*) GAS will not bump passed sparclite by default, an option must be passed to enable the v9 instructions.

GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested.  SPARC v9 is always incompatible with sparclite.

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite

-Av8plus | -Av8plusa | -Av9 | -Av9a

Use one of the -A options to select one of the SPARC architectures explicitly.  If you select an architecture explicitly, as reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level.

-Av8plus and -Av8plusa select a 32 bit environment.

-Av9 and -Av9a select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.

-Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.

-xarch=v8plus | -xarch=v8plusa

For compatibility with the Solaris v9 assembler.  These options are equivalent to -Av8plus and -Av8plusa, respectively.

-bump

Warn whenever it is necessary to switch to another level.  If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).

-32 | -64

Select the word size, either 32 bits or 64 bits.  These options are only available with the ELF object file format, and require that the necessary BFD support has been included.


Enforcing aligned data
Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent

Enforcing aligned data

SPARC GAS normally permits data to be misaligned.  For example, it permits the .long pseudo-op to be used on a byte boundary.  However, the native SunOS and Solaris assemblers issue an error when they see misaligned data.

You can use the --enforce-aligned-data option to make SPARC GAS also issue an error about misaligned data, just as the SunOS and Solaris assemblers do.

The --enforce-aligned-data option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed data structures (structures defined using the packed attribute).  You may have to assemble with GAS in order to initialize packed data structures in your own code.


Floating Point
Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent

Floating Point

The Sparc uses IEEE floating-point numbers.


Sparc Machine Directives
Node: Sparc-Directives, Next: , Prev: Sparc-Float, Up: Sparc-Dependent

Sparc Machine Directives

The Sparc version of as supports the following additional machine directives:

.align

This must be followed by the desired alignment in bytes.

.common

This must be followed by a symbol name, a positive number, and "bss".  This behaves somewhat like .comm, but the syntax is different.

.half

This is functionally identical to .short.

.proc

This directive is ignored.  Any text following it on the same line is also ignored.

.reserve

This must be followed by a symbol name, a positive number, and "bss".  This behaves somewhat like .lcomm, but the syntax is different.

.seg

This must be followed by "text", "data", or "data1".  It behaves like .text, .data, or .data 1.

.skip

This is functionally identical to the .space directive.

.word

On the Sparc, the .word directive produces 32 bit values, instead of the 16 bit values it produces on many other machines.

.xword

On the Sparc V9 processor, the .xword directive produces 64 bit values.


Z8000 Dependent Features
Node: Z8000-Dependent, Next: Vax-Dependent, Prev: V850-Dependent, Up: Machine Dependencies

Z8000 Dependent Features

The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.

When the assembler is in unsegmented mode (specified with the unsegm directive), an address takes up one word (16 bit) sized register.  When the assembler is in segmented mode (specified with the segm directive), a 24-bit address takes up a long (32 bit) register.  See Assembler Directives for the Z8000, for a list of other Z8000 specific assembler directives.

* Menu:

Z8000 Options	No special command-line options for Z8000

Z8000 Syntax	Assembler syntax for the Z8000

Z8000 Directives	Special directives for the Z8000

Z8000 Opcodes	Opcodes


Options
Node: Z8000 Options, Next: Z8000 Syntax, Prev: , Up: Z8000-Dependent

Options

as has no additional command-line options for the Zilog Z8000 family.


Syntax
Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent

Syntax

* Menu:

Z8000-Chars	Special Characters

Z8000-Regs	Register Names

Z8000-Addressing	Addressing Modes


Special Characters
Node: Z8000-Chars, Next: Z8000-Regs, Prev: , Up: Z8000 Syntax

Special Characters

! is the line comment character.

You can use ; instead of a newline to separate statements.


Register Names
Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax

Register Names

The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can refer to different sized groups of registers by register number, with the prefix r for 16 bit registers, rr for 32 bit registers and rq for 64 bit registers.  You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes.  They are named rnh and rnl.

byte registers

r0l r0h r1h r1l r2h r2l r3h r3l
r4h r4l r5h r5l r6h r6l r7h r7l

word registers

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

long word registers

rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14

quad word registers

rq0 rq4 rq8 rq12


Addressing Modes
Node: Z8000-Addressing, Next: , Prev: Z8000-Regs, Up: Z8000 Syntax

Addressing Modes

as understands the following addressing modes for the Z8000:

rn

Register direct

@rn

Indirect register

addr

Direct: the 16 bit or 24 bit address (depending on whether the assembler is in segmented or unsegmented mode) of the operand is in the instruction.

address(rn)

Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand.

rn(#imm)

Base Address: the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand.

rn(rm)

Base Index: the 16 or 24 bit register rn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand.

#xx

Immediate data xx.


Assembler Directives for the Z8000
Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent

Assembler Directives for the Z8000

The Z8000 port of as includes these additional assembler directives, for compatibility with other Z8000 assemblers.  As shown, these do not begin with . (unlike the ordinary as directives).

segm

Generates code for the segmented Z8001.

unsegm

Generates code for the unsegmented Z8002.

name

Synonym for .file

global

Synonym for .global

wval

Synonym for .word

lval

Synonym for .long

bval

Synonym for .byte

sval

Assemble a string.  sval expects one string literal, delimited by single quotes.  It assembles each byte of the string into consecutive addresses.  You can use the escape sequence %xx (where xx represents a two-digit hexadecimal number) to represent the character whose ASCII value is xx.  Use this feature to describe single quote and other characters that may not appear in string literals as themselves.  For example, the C statement char *a = "he said \"it's 50% off\""; is represented in Z8000 assembly language (shown with the assembler output in hex at the left) as

68652073    sval    'he said %22it%27s 50%25 off%22%00'
61696420
22697427
73203530
25206F66
662200

rsect

synonym for .section

block

synonym for .space

even

special case of .align; aligns output to even byte boundary.


Opcodes
Node: Z8000 Opcodes, Next: , Prev: Z8000 Directives, Up: Z8000-Dependent

Opcodes

For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.

The following table summarizes the opcodes and their arguments:

            rs   16 bit source register
            rd   16 bit destination register
            rbs   8 bit source register
            rbd   8 bit destination register
            rrs   32 bit source register
            rrd   32 bit destination register
            rqs   64 bit source register
            rqd   64 bit destination register
            addr 16/24 bit address
            imm  immediate data

adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
add rd,@rs              clrb rbd                dab rbd
add rd,addr             com @rd                 dbjnz rbd,disp7
add rd,addr(rs)         com addr                dec @rd,imm4m1
add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
add rd,rs               com rd                  dec addr,imm4m1
addb rbd,@rs            comb @rd                dec rd,imm4m1
addb rbd,addr           comb addr               decb @rd,imm4m1
addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
addb rbd,imm8           comb rbd                decb addr,imm4m1
addb rbd,rbs            comflg flags            decb rbd,imm4m1
addl rrd,@rs            cp @rd,imm16            di i2
addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
addl rrd,rrs            cp rd,addr              div rrd,imm16
and rd,@rs              cp rd,addr(rs)          div rrd,rs
and rd,addr             cp rd,imm16             divl rqd,@rs
and rd,addr(rs)         cp rd,rs                divl rqd,addr
and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
andb rbd,addr(rs)       cpb rbd,addr            ei i2
andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
andb rbd,rbs            cpb rbd,imm8            ex rd,addr
bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
bitb rbd,rs             cpl rrd,@rs             ext8f imm8
bpt                     cpl rrd,addr            exts rrd
call @rd                cpl rrd,addr(rs)        extsb rd
call addr               cpl rrd,imm32           extsl rqd
call addr(rd)           cpl rrd,rrs             halt
calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
iret                    ldib @rd,@rs,rr         neg addr(rd)
jp cc,@rd               ldir @rd,@rs,rr         neg rd
jp cc,addr              ldirb @rd,@rs,rr        negb @rd
jp cc,addr(rd)          ldk rd,imm4             negb addr
jr cc,disp8             ldl @rd,rrs             negb addr(rd)
ld @rd,imm16            ldl addr(rd),rrs        negb rbd
ld @rd,rs               ldl addr,rrs            nop
ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
ld addr,rs              ldl rrd,addr            or rd,imm16
ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
ld rd,@rs               ldl rrd,rrs             orb rbd,addr
ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
ldb rbd,@rs             mbit                    popl addr,@rs
ldb rbd,addr            mreq rd                 popl rrd,@rs
ldb rbd,addr(rs)        mres                    push @rd,@rs
ldb rbd,imm8            mset                    push @rd,addr
ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
push @rd,rs             set addr,imm4           subl rrd,imm32
pushl @rd,@rs           set rd,imm4             subl rrd,rrs
pushl @rd,addr          set rd,rs               tcc cc,rd
pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
pushl @rd,rrs           setb addr(rd),imm4      test @rd
res @rd,imm4            setb addr,imm4          test addr
res addr(rd),imm4       setb rbd,imm4           test addr(rd)
res addr,imm4           setb rbd,rs             test rd
res rd,imm4             setflg imm4             testb @rd
res rd,rs               sinb rbd,imm16          testb addr
resb @rd,imm4           sinb rd,imm16           testb addr(rd)
resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
resb addr,imm4          sindb @rd,@rs,rba       testl @rd
resb rbd,imm4           sinib @rd,@rs,ra        testl addr
resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
resflg imm4             sla rd,imm8             testl rrd
ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
rsvd36                  sra rd,imm8             tset rd
rsvd38                  srab rbd,imm8           tsetb @rd
rsvd78                  sral rrd,imm8           tsetb addr
rsvd7e                  srl rd,imm8             tsetb addr(rd)
rsvd9d                  srlb rbd,imm8           tsetb rbd
rsvd9f                  srll rrd,imm8           xor rd,@rs
rsvdb9                  sub rd,@rs              xor rd,addr
rsvdbf                  sub rd,addr             xor rd,addr(rs)
sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
sbcb rbd,rbs            sub rd,imm16            xor rd,rs
sc imm8                 sub rd,rs               xorb rbd,@rs
sda rd,rs               subb rbd,@rs            xorb rbd,addr
sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
sdll rrd,rs             subl rrd,@rs
set @rd,imm4            subl rrd,addr
set addr(rd),imm4       subl rrd,addr(rs)


VAX Dependent Features
Node: Vax-Dependent, Next: , Prev: Z8000-Dependent, Up: Machine Dependencies

VAX Dependent Features

* Menu:

VAX-Opts	VAX Command-Line Options

VAX-float	VAX Floating Point

VAX-directives	Vax Machine Directives

VAX-opcodes	VAX Opcodes

VAX-branch	VAX Branch Improvement

VAX-operands	VAX Operands

VAX-no	Not Supported on VAX


VAX Command-Line Options
Node: VAX-Opts, Next: VAX-float, Prev: , Up: Vax-Dependent

VAX Command-Line Options

The Vax version of as accepts any of the following options, gives a warning message that the option was ignored and proceeds.  These options are for compatibility with scripts designed for other people's assemblers.

-D (Debug)

-S (Symbol Table)

-T (Token Trace)

These are obsolete options used to debug old assemblers.

-d (Displacement size for JUMPs)

This option expects a number following the -d.  Like options that expect filenames, the number may immediately follow the -d (old standard) or constitute the whole of the command line argument that follows -d (GNU standard).

-V (Virtualize Interpass Temporary File)

Some other assemblers use a temporary file.  This option commanded them to keep the information in active memory rather than in a disk file.  as always does this, so this option is redundant.

-J (JUMPify Longer Branches)

Many 32-bit computers permit a variety of branch instructions to do the same job.  Some of these instructions are short (and fast) but have a limited range; others are long (and slow) but can branch anywhere in virtual memory.  Often there are 3 flavors of branch: short, medium and long.  Some other assemblers would emit short and medium branches, unless told by this option to emit short and long branches.

-t (Temporary File Directory)

Some other assemblers may use a temporary file, and this option takes a filename being the directory to site the temporary file.  Since as does not use a temporary disk file, this option makes no difference.  -t needs exactly one filename.

The Vax version of the assembler accepts two options when compiled for VMS.  They are -h, and -+.  The -h option prevents as from modifying the symbol-table entries for symbols that contain lowercase characters (I think).  The -+ option causes as to print warning messages if the FILENAME part of the object file, or any symbol name is larger than 31 characters.  The -+ option also inserts some code following the _main symbol so that the object file is compatible with Vax-11 "C".


VAX Floating Point
Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent

VAX Floating Point

Conversion of flonums to floating point is correct, and compatible with previous assemblers.  Rounding is towards zero if the remainder is exactly half the least significant bit.

D, F, G and H floating point formats are understood.

Immediate floating literals (e.g. S`$6.9) are rendered correctly.  Again, rounding is towards zero in the boundary case.

The .float directive produces f format numbers.  The .double directive produces d format numbers.


Vax Machine Directives
Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent

Vax Machine Directives

The Vax version of the assembler supports four directives for generating Vax floating point constants.  They are described in the table below.

.dfloat

This expects zero or more flonums, separated by commas, and assembles Vax d format 64-bit floating point constants.

.ffloat

This expects zero or more flonums, separated by commas, and assembles Vax f format 32-bit floating point constants.

.gfloat

This expects zero or more flonums, separated by commas, and assembles Vax g format 64-bit floating point constants.

.hfloat

This expects zero or more flonums, separated by commas, and assembles Vax h format 128-bit floating point constants.


VAX Opcodes
Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent

VAX Opcodes

All DEC mnemonics are supported.  Beware that case...  instructions have exactly 3 operands.  The dispatch table that follows the case... instruction should be made with .word statements.  This is compatible with all unix assemblers we know of.


VAX Branch Improvement
Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent

VAX Branch Improvement

Certain pseudo opcodes are permitted.  They are for branch instructions.  They expand to the shortest branch instruction that reaches the target.  Generally these mnemonics are made by substituting j for b at the start of a DEC mnemonic.  This feature is included both for compatibility and to help compilers.  If you do not need this feature, avoid these opcodes.  Here are the mnemonics, and the code they can expand into.

jbsb

Jsb is already an instruction mnemonic, so we chose jbsb.

(byte displacement)

bsbb ...

(word displacement)

bsbw ...

(long displacement)

jsb ...

jbr

jr

Unconditional branch.

(byte displacement)

brb ...

(word displacement)

brw ...

(long displacement)

jmp ...

jCOND

COND may be any one of the conditional branches neq, nequ, eql, eqlu, gtr, geq, lss, gtru, lequ, vc, vs, gequ, cc, lssu, cs.  COND may also be one of the bit tests bs, bc, bss, bcs, bsc, bcc, bssi, bcci, lbs, lbc.  NOTCOND is the opposite condition to COND.

(byte displacement)

bCOND ...

(word displacement)

bNOTCOND foo ; brw ... ; foo:

(long displacement)

bNOTCOND foo ; jmp ... ; foo:

jacbX

X may be one of b d f g h l w.

(word displacement)

OPCODE ...

(long displacement)

OPCODE ..., foo ;
brb bar ;
foo: jmp ... ;
bar:

jaobYYY

YYY may be one of lss leq.

jsobZZZ

ZZZ may be one of geq gtr.

(byte displacement)

OPCODE ...

(word displacement)

OPCODE ..., foo ;
brb bar ;
foo: brw destination ;
bar:

(long displacement)

OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:

aobleq

aoblss

sobgeq

sobgtr

(byte displacement)

OPCODE ...

(word displacement)

OPCODE ..., foo ;
brb bar ;
foo: brw destination ;
bar:

(long displacement)

OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:


VAX Operands
Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent

VAX Operands

The immediate character is $ for Unix compatibility, not # as DEC writes it.

The indirect character is * for Unix compatibility, not @ as DEC writes it.

The displacement sizing character is ` (an accent grave) for Unix compatibility, not ^ as DEC writes it.  The letter preceding ` may have either case.  G is not understood, but all other letters (b i l s w) are understood.

Register names understood are r0 r1 r2 ... r15 ap fp sp pc.  Upper and lower case letters are equivalent.

For instance

tstb *w`$4(r5)

Any expression is permitted in an operand.  Operands are comma separated.


Not Supported on VAX
Node: VAX-no, Next: , Prev: VAX-operands, Up: Vax-Dependent

Not Supported on VAX

Vax bit fields can not be assembled with as.  Someone can add the required code if they really need it.


v850 Dependent Features
Node: V850-Dependent, Next: Z8000-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies

v850 Dependent Features

* Menu:

V850 Options	Options

V850 Syntax	Syntax

V850 Floating Point	Floating Point

V850 Directives	V850 Machine Directives

V850 Opcodes	Opcodes


Options
Node: V850 Options, Next: V850 Syntax, Prev: , Up: V850-Dependent

Options

as supports the following additional command-line options for the V850 processor family:

-wsigned_overflow

Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes.  By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.

-wunsigned_overflow

Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes.  By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.

-mv850

Specifies that the assembled code should be marked as being targeted at the V850 processor.  This allows the linker to detect attempts to link such code with code assembled for other processors.


Syntax
Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent

Syntax

* Menu:

V850-Chars	Special Characters

V850-Regs	Register Names


Special Characters
Node: V850-Chars, Next: V850-Regs, Prev: , Up: V850 Syntax

Special Characters

# is the line comment character.


Register Names
Node: V850-Regs, Next: , Prev: V850-Chars, Up: V850 Syntax

Register Names

as supports the following names for registers:

general register 0

r0, zero

general register 1

r1

general register 2

r2, hp

general register 3

r3, sp

general register 4

r4, gp

general register 5

r5, tp

general register 6

r6

general register 7

r7

general register 8

r8

general register 9

r9

general register 10

r10

general register 11

r11

general register 12

r12

general register 13

r13

general register 14

r14

general register 15

r15

general register 16

r16

general register 17

r17

general register 18

r18

general register 19

r19

general register 20

r20

general register 21

r21

general register 22

r22

general register 23

r23

general register 24

r24

general register 25

r25

general register 26

r26

general register 27

r27

general register 28

r28

general register 29

r29

general register 30

r30, ep

general register 31

r31, lp

system register 0

eipc

system register 1

eipsw

system register 2

fepc

system register 3

fepsw

system register 4

ecr

system register 5

psw


Floating Point
Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent

Floating Point

The V850 family uses IEEE floating-point numbers.


V850 Machine Directives
Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent

V850 Machine Directives

.offset <expression>

Moves the offset into the current section to the specified amount.

.section "name", <type>

This is an extension to the standard .section directive.  It sets the current section to be <type> and creates an alias for this section called "name".

.v850

Specifies that the assembled code should be marked as being targeted at the V850 processor.  This allows the linker to detect attempts to link such code with code assembled for other processors.


Opcodes
Node: V850 Opcodes, Next: , Prev: V850 Directives, Up: V850-Dependent

Opcodes

as implements all the standard V850 opcodes.

{No Value For "rd{}AS"} also implements the following pseudo ops:

hi0()

Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction.  For example:

mulhi hi0(here - there), r5, r6

computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then mutliplies it by the lower 16 bits in register 5, putting the result into register 6.

lo()

Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction.  For example:

addi lo(here - there), r5, r6

computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6.

hi()

Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction.  For example the following code can be used to compute the address of the label 'here' and store it into register 6:

movhi hi(here), r0, r6     movea lo(here), r6, r6

The reason for this special behaviour is that movea performs a sign extention on its immediate operand.  So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).  With the hi() pseudo op adding in the top bit of the lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right value.

sdaoff()

Computes the offset of the named variable from the start of the Small Data Area (whoes address is held in register 4, the GP register) and stores the result as a 16 bit signed value in the immediate operand field of the given instruction.  For example:

ld.w sdaoff(_a_variable)[gp],r6

loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +/- 32K of the address held in the GP register.  [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'.  This can either be set up automatically by the linker, or specifically set by using the --defsym __gp=<value> command line option].

tdaoff()

Computes the offset of the named variable from the start of the Tiny Data Area (whoes address is held in register 30, the EP register) and stores the result as a 7 or 8 bit unsigned value in the immediate operand field of the given instruction.  For example:

sld.w tdaoff(_a_variable)[ep],r6

loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +256 bytes of the address held in the EP register.  [Note the linker assumes that the EP register contains a fixed address set to the address of the label called '__ep'.  This can either be set up automatically by the linker, or specifically set by using the --defsym __ep=<value> command line option].

zdaoff()

Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction.  For example:

movea zdaoff(_a_variable),zero,r6

puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of memory.  (Strictly speaking it also possible to access the last 32K of memory as well, as the offsets are signed).

For information on the V850 instruction set, see V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC.  Ltd.


Reporting Bugs
Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top

Reporting Bugs

Your bug reports play an essential role in making as reliable.

Reporting a bug may help you by bringing a solution to your problem, or it may not.  But in any case the principal function of a bug report is to help the entire community by making the next version of as work better.  Bug reports are your contribution to the maintenance of as.

In order for a bug report to serve its purpose, you must include the information that enables us to fix the bug.

* Menu:

Bug Criteria	Have you found a bug?

Bug Reporting	How to report bugs


Have you found a bug?
Node: Bug Criteria, Next: Bug Reporting, Prev: , Up: Reporting Bugs

Have you found a bug?

If you are not sure whether you have found a bug, here are some guidelines:

•	If the assembler gets a fatal signal, for any input whatever, that is a as bug.  Reliable assemblers never crash.

•	If as produces an error message for valid input, that is a bug.

•	If as does not produce an error message for invalid input, that is a bug.  However, you should note that your idea of "invalid input" might be our idea of "an extension" or "support for traditional practice".

•	If you are an experienced user of assemblers, your suggestions for improvement of as are welcome in any case.


How to report bugs
Node: Bug Reporting, Next: , Prev: Bug Criteria, Up: Reporting Bugs

How to report bugs

A number of companies and individuals offer support for GNU products.  If you obtained as from a support organization, we recommend you contact that organization first.

You can find contact information for many support companies and individuals in the file etc/SERVICE in the GNU Emacs distribution.

In any event, we also recommend that you send bug reports for as to bug-gnu-utils@prep.ai.mit.edu.

The fundamental principle of reporting bugs usefully is this: report all the facts.  If you are not sure whether to state a fact or leave it out, state it!

Often people omit facts because they think they know what causes the problem and assume that some details do not matter.  Thus, you might assume that the name of a symbol you use in an example does not matter.  Well, probably it does not, but one cannot be sure.  Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory; perhaps, if the name were different, the contents of that location would fool the assembler into doing the right thing despite the bug.  Play it safe and give a specific, complete example.  That is the easiest thing for you to do, and the most helpful.

Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us.  Therefore, always write your bug reports on the assumption that the bug has not been reported previously.

Sometimes people give a few sketchy facts and ask, "Does this ring a bell?"  Those bug reports are useless, and we urge everyone to refuse to respond to them except to chide the sender to report bugs properly.

To enable us to fix the bug, you should include all these things:

•	The version of as.  as announces it if you start it with the --version argument.

Without this, we will not know whether there is any point in looking for the bug in the current version of as.

•	Any patches you may have applied to the as source.

•	The type of machine you are using, and the operating system name and version number.

•	What compiler (and its version) was used to compile as--e.g.  "gcc-2.7".

•	The command arguments you gave the assembler to assemble your example and observe the bug.  To guarantee you will not omit something important, list them all.  A copy of the Makefile (or the output from make) is sufficient.

If we were to try to guess the arguments, we would probably guess wrong and then we might not encounter the bug.

•	A complete input file that will reproduce the bug.  If the bug is observed when the assembler is invoked via a compiler, send the assembler source, not the high level language source.  Most compilers will produce the assembler source when run with the -S option.  If you are using gcc, use the options -v --save-temps; this will save the assembler source in a file with an extension of .s, and also show you exactly how as is being run.

•	A description of what behavior you observe that you believe is incorrect.  For example, "It gets a fatal signal."

Of course, if the bug is that as gets a fatal signal, then we will certainly notice it.  But if the bug is incorrect output, we might not notice unless it is glaringly wrong.  You might as well not give us a chance to make a mistake.

Even if the problem you experience is a fatal signal, you should still say so explicitly.  Suppose something strange is going on, such as, your copy of as is out of synch, or you have encountered a bug in the C library on your system.  (This has happened!)  Your copy might crash and ours would not.  If you told us to expect a crash, then when ours fails to crash, we would know that the bug was not happening for us.  If you had not told us to expect a crash, then we would not be able to draw any conclusion from our observations.

•	If you wish to suggest changes to the as source, send us context diffs, as generated by diff with the -u, -c, or -p option.  Always send diffs from the old file to the new file.  If you even discuss something in the as source, refer to it by context, not by line number.

The line numbers in our development sources will not match those in your sources.  Your line numbers would convey no useful information to us.

Here are some things that are not necessary:

•	A description of the envelope of the bug.

Often people who encounter a bug spend a lot of time investigating which changes to the input file will make the bug go away and which changes will not affect it.

This is often time consuming and not very useful, because the way we will find the bug is by running a single example under the debugger with breakpoints, not by pure deduction from a series of examples.  We recommend that you save your time for something else.

Of course, if you can find a simpler example to report instead of the original one, that is a convenience for us.  Errors in the output will be easier to spot, running under the debugger will take less time, and so on.

However, simplification is not vital; if you do not want to do this, report the bug anyway and send us the entire test case you used.

•	A patch for the bug.

A patch for the bug does help us if it is a good one.  But do not omit the necessary information, such as the test case, on the assumption that a patch is all we need.  We might see problems with your patch and decide to fix the problem another way, or we might not understand it at all.

Sometimes with a program as complicated as as it is very hard to construct an example that will make the program follow a certain path through the code.  If you do not send us the example, we will not be able to construct one, so we will not be able to verify that the bug is fixed.

And if we cannot understand what bug you are trying to fix, or why your patch should be an improvement, we will not install it.  A test case will help us to understand.

•	A guess about what the bug is or what it depends on.

Such guesses are usually wrong.  Even we cannot guess right about such things without first using the debugger to find the facts.


Acknowledgements
Node: Acknowledgements, Next: Index, Prev: Reporting Bugs, Up: Top

Acknowledgements

If you have contributed to as and your name isn't listed here, it is not meant as a slight.  We just don't know about it.  Send mail to the maintainer, and we'll correct the situation.  Currently the maintainer is Ken Raeburn (email address raeburn@cygnus.com).

Dean Elsner wrote the original GNU assembler for the VAX.(1)

Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug information and the 68k series machines, most of the preprocessing pass, and extensive changes in messages.c, input-file.c, write.c.

K. Richard Pixley maintained GAS for a while, adding various enhancements and many bug fixes, including merging support for several processors, breaking GAS up to handle multiple object file format back ends (including heavy rewrite, testing, an integration of the coff and b.out back ends), adding configuration including heavy testing and verification of cross assemblers and file splits and renaming, converted GAS to strictly ANSI C including full prototypes, added support for m680[34]0 and cpu32, did considerable work on i960 including a COFF port (including considerable amounts of reverse engineering), a SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host ports, updated "know" assertions and made them work, much other reorganization, cleanup, and lint.

Ken Raeburn wrote the high-level BFD interface code to replace most of the code in format-specific I/O modules.

The original VMS support was contributed by David L. Kashtan.  Eric Youngdale has done much work with it since.

The Intel 80386 machine description was written by Eliot Dresselhaus.

Minh Tran-Le at IntelliCorp contributed some AIX 386 support.

The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science.

Keith Knowles at the Open Software Foundation wrote the original MIPS back end (tc-mips.c, tc-mips.h), and contributed Rose format support (which hasn't been merged in yet).  Ralph Campbell worked with the MIPS code to support a.out format.

Support for the Zilog Z8k and Hitachi H8/300 and H8/500 processors (tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format (obj-ieee), was written by Steve Chamberlain of Cygnus Support.  Steve also modified the COFF back end to use BFD for some low-level operations, for use with the H8/300 and AMD 29k targets.

John Gilmore built the AMD 29000 support, added .include support, and simplified the configuration of which versions accept which directives.  He updated the 68k machine description so that Motorola's opcodes always produced fixed-size instructions (e.g. jsr), while synthetic instructions remained shrinkable (jbsr).  John fixed many bugs, including true tested cross-compilation support, and one bug in relaxation that took a week and required the proverbial one-bit fix.

Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and PowerPC assembler, and made a few other minor patches.

Steve Chamberlain made as able to generate listings.

Hewlett-Packard contributed support for the HP9000/300.

Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF object formats).  This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support.

Support for ELF format files has been worked on by Mark Eichin of Cygnus Support (original, incomplete implementation for SPARC), Pete Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, and some initial 64-bit support).

Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha.

Several engineers at Cygnus Support have also provided many small bug fixes and configuration enhancements.

Many others have contributed large or small bugfixes and enhancements.  If you have contributed significant work and are not mentioned on this list, and want to be, let us know.  Some of the history has been lost; we are not intentionally leaving anyone out.


Any more details?


Index
Node: Index, Next: , Prev: Acknowledgements, Up: Top

Index

#:	Comments.

#APP:	Preprocessing.

#NO_APP:	Preprocessing.

-:	Command Line.

-enforce-aligned-data:	Sparc-Aligned-Data.

-MD:	MD.

-statistics:	statistics.

-a:	a.

-ac:	a.

-ad:	a.

-ah:	a.

-al:	a.

-an:	a.

-as:	a.

-Asparclet:	Sparc-Opts.

-Asparclite:	Sparc-Opts.

-Av6:	Sparc-Opts.

-Av8:	Sparc-Opts.

-Av9:	Sparc-Opts.

-Av9a:	Sparc-Opts.

-D:	D.

-f:	f.

-I path:	I.

-K:	K.

-L:	L.

-M:	M.

-o:	o.

-R:	R.

-v:	v.

-version:	v.

-W:	W.

.o:	Object.

-bit code, i386:	i386-16bit.

K support:	AMD29K-Dependent.

@word modifier, D10V:	D10V-Word.

$ in symbol names <1>:	SH-Chars.

$ in symbol names <2>:	H8/500-Chars.

$ in symbol names:	D10V-Chars.

-+ option, VAX/VMS:	VAX-Opts.

-A options, i960:	Options-i960.

-b option, i960:	Options-i960.

-D, ignored on VAX:	VAX-Opts.

-d, VAX option:	VAX-Opts.

-EB command line option, ARM:	ARM Options.

-EB option (MIPS):	MIPS Opts.

-EL command line option, ARM:	ARM Options.

-EL option (MIPS):	MIPS Opts.

-G option (MIPS):	MIPS Opts.

-h option, VAX/VMS:	VAX-Opts.

-J, ignored on VAX:	VAX-Opts.

-mall command line option, ARM:	ARM Options.

-mapcs command line option, ARM:	ARM Options.

-marmv command line option, ARM:	ARM Options.

-marm command line option, ARM:	ARM Options.

-mbig-endian option (ARC):	ARC-Opts.

-mfpa command line option, ARM:	ARM Options.

-mfpe-old command line option, ARM:	ARM Options.

-mlittle-endian option (ARC):	ARC-Opts.

-mno-fpu command line option, ARM:	ARM Options.

-mthumb-interwork command line option, ARM:	ARM Options.

-mthumb command line option, ARM:	ARM Options.

-mv850 command line option, V850:	V850 Options.

-no-relax option, i960:	Options-i960.

-nocpp ignored (MIPS):	MIPS Opts.

-S, ignored on VAX:	VAX-Opts.

-T, ignored on VAX:	VAX-Opts.

-V, redundant on VAX:	VAX-Opts.

-wsigned_overflow command line option, V850:	V850 Options.

-wunsigned_overflow command line option, V850:	V850 Options.

.insn:	MIPS insn.

.param on HPPA:	HPPA Directives.

.set autoextend:	MIPS autoextend.

.set mipsn:	MIPS ISA.

.set noautoextend:	MIPS autoextend.

.set pop:	MIPS option stack.

.set push:	MIPS option stack.

.v850 directive, V850:	V850 Directives.

. (symbol):	Dot.

: (label):	Statements.

\" (doublequote character):	Strings.

\ddd (octal character code):	Strings.

\xd... (hex character code):	Strings.

\\ (\ character):	Strings.

\b (backspace character):	Strings.

\f (formfeed character):	Strings.

\n (newline character):	Strings.

\r (carriage return character):	Strings.

\t (tab):	Strings.

a.out symbol attributes:	a.out Symbols.

ABORT directive:	ABORT.

abort directive:	Abort.

align directive:	Align.

align directive, SPARC:	Sparc-Directives.

app-file directive:	App-File.

arm directive, ARM:	ARM Directives.

ascii directive:	Ascii.

asciz directive:	Asciz.

balignl directive:	Balign.

balignw directive:	Balign.

balign directive:	Balign.

block directive, AMD 29K:	AMD29K Directives.

bss directive, i960:	Directives-i960.

byte directive:	Byte.

callj, i960 pseudo-opcode:	callj-i960.

code16 directive, i386:	i386-16bit.

code32 directive, i386:	i386-16bit.

code directive, ARM:	ARM Directives.

common directive, SPARC:	Sparc-Directives.

comm directive:	Comm.

cputype directive, AMD 29K:	AMD29K Directives.

cpu directive, SPARC:	ARC-Directives.

data1 directive, M680x0:	M68K-Directives.

data2 directive, M680x0:	M68K-Directives.

data directive:	Data.

def directive:	Def.

desc directive:	Desc.

dfloat directive, VAX:	VAX-directives.

dim directive:	Dim.

double directive:	Double.

double directive, i386:	i386-Float.

double directive, M680x0:	M68K-Float.

double directive, VAX:	VAX-float.

ecr register, V850:	V850-Regs.

eipc register, V850:	V850-Regs.

eipsw register, V850:	V850-Regs.

eject directive:	Eject.

else directive:	Else.

endef directive:	Endef.

endif directive:	Endif.

endm directive:	Macro.

ep register, V850:	V850-Regs.

equiv directive:	Equiv.

equ directive:	Equ.

err directive:	Err.

even directive, M680x0:	M68K-Directives.

exitm directive:	Macro.

extended directive, i960:	Directives-i960.

extend directive M680x0:	M68K-Float.

extern directive:	Extern.

fepc register, V850:	V850-Regs.

fepsw register, V850:	V850-Regs.

ffloat directive, VAX:	VAX-directives.

file directive:	File.

file directive, AMD 29K:	AMD29K Directives.

fill directive:	Fill.

float directive:	Float.

float directive, i386:	i386-Float.

float directive, M680x0:	M68K-Float.

float directive, VAX:	VAX-float.

force_thumb directive, ARM:	ARM Directives.

gbr960, i960 postprocessor:	Options-i960.

gfloat directive, VAX:	VAX-directives.

global directive:	Global.

gp register, MIPS:	MIPS Object.

gp register, V850:	V850-Regs.

half directive, SPARC:	Sparc-Directives.

hfloat directive, VAX:	VAX-directives.

hi0 pseudo-op, V850:	V850 Opcodes.

hi pseudo-op, V850:	V850 Opcodes.

hword directive:	hword.

ident directive:	Ident.

ifdef directive:	If.

ifndef directive:	If.

ifnotdef directive:	If.

if directive:	If.

imul instruction, i386:	i386-Notes.

include directive:	Include.

include directive search path:	I.

int directive:	Int.

int directive, H8/300:	H8/300 Directives.

int directive, H8/500:	H8/500 Directives.

int directive, i386:	i386-Float.

irpc directive:	Irpc.

irp directive:	Irp.

lcomm directive:	Lcomm.

ldouble directive M680x0:	M68K-Float.

leafproc directive, i960:	Directives-i960.

lflags directive (ignored):	Lflags.

line directive:	Line.

line directive, AMD 29K:	AMD29K Directives.

linkonce directive:	Linkonce.

list directive:	List.

ln directive:	Ln.

long directive:	Long.

long directive, i386:	i386-Float.

lo pseudo-op, V850:	V850 Opcodes.

lp register, V850:	V850-Regs.

macro directive:	Macro.

mri directive:	MRI.

mul instruction, i386:	i386-Notes.

nolist directive:	Nolist.

octa directive:	Octa.

offset directive, V850:	V850 Directives.

org directive:	Org.

p2alignl directive:	P2align.

p2alignw directive:	P2align.

p2align directive:	P2align.

proc directive, SPARC:	Sparc-Directives.

psize directive:	Psize.

psw register, V850:	V850-Regs.

quad directive:	Quad.

quad directive, i386:	i386-Float.

rept directive:	Rept.

reserve directive, SPARC:	Sparc-Directives.

sbttl directive:	Sbttl.

scl directive:	Scl.

sdaoff pseudo-op, V850:	V850 Opcodes.

section directive:	Section.

section directive, V850:	V850 Directives.

sect directive, AMD 29K:	AMD29K Directives.

seg directive, SPARC:	Sparc-Directives.

set directive:	Set.

short directive:	Short.

single directive:	Single.

single directive, i386:	i386-Float.

size directive:	Size.

skip directive:	Skip.

skip directive, M680x0:	M68K-Directives.

skip directive, SPARC:	Sparc-Directives.

sleb128 directive:	Sleb128.

space directive:	Space.

sp register, V850:	V850-Regs.

stabx directives:	Stab.

stabd directive:	Stab.

stabn directive:	Stab.

stabs directive:	Stab.

string directive:	String.

string directive on HPPA:	HPPA Directives.

symver directive:	Symver.

sysproc directive, i960:	Directives-i960.

tag directive:	Tag.

tdaoff pseudo-op, V850:	V850 Opcodes.

text directive:	Text.

tfloat directive, i386:	i386-Float.

thumb_func directive, ARM:	ARM Directives.

thumb directive, ARM:	ARM Directives.

title directive:	Title.

tp register, V850:	V850-Regs.

type directive:	Type.

ualong directive, SH:	SH Directives.

uaword directive, SH:	SH Directives.

uleb128 directive:	Uleb128.

use directive, AMD 29K:	AMD29K Directives.

val directive:	Val.

word directive:	Word.

word directive, H8/300:	H8/300 Directives.

word directive, H8/500:	H8/500 Directives.

word directive, i386:	i386-Float.

word directive, SPARC:	Sparc-Directives.

xword directive, SPARC:	Sparc-Directives.

zdaoff pseudo-op, V850:	V850 Opcodes.

zero register, V850:	V850-Regs.

-base-size-default-16:	M68K-Opts.

-base-size-default-32:	M68K-Opts.

-bitwise-or option, M680x0:	M68K-Opts.

-disp-size-default-16:	M68K-Opts.

-disp-size-default-32:	M68K-Opts.

-register-prefix-optional option, M680x0:	M68K-Opts.

-l option, M680x0:	M68K-Opts.

-m68000 and related options:	M68K-Opts.

mit:	M68K-Syntax.

a.out:	Object.

absolute section:	Ld Sections.

addition, permitted arguments:	Infix Ops.

addresses:	Expressions.

addresses, format of:	Secs Background.

addressing modes, D10V:	D10V-Addressing.

addressing modes, H8/300:	H8/300-Addressing.

addressing modes, H8/500:	H8/500-Addressing.

addressing modes, M680x0:	M68K-Syntax.

addressing modes, SH:	SH-Addressing.

addressing modes, Z8000:	Z8000-Addressing.

advancing location counter:	Org.

altered difference tables:	Word.

alternate syntax for the 680x0:	M68K-Moto-Syntax.

AMD 29K floating point (ieee):	AMD29K Floating Point.

AMD 29K identifiers:	AMD29K-Chars.

AMD 29K line comment character:	AMD29K-Chars.

AMD 29K machine directives:	AMD29K Directives.

AMD 29K macros:	AMD29K-Macros.

AMD 29K opcodes:	AMD29K Opcodes.

AMD 29K options (none):	AMD29K Options.

AMD 29K protected registers:	AMD29K-Regs.

AMD 29K register names:	AMD29K-Regs.

AMD 29K special purpose registers:	AMD29K-Regs.

AMD 29K support:	AMD29K-Dependent.

ARC architectures:	ARC-Opts.

ARC big-endian output:	ARC-Opts.

ARC endianness:	Overview.

ARC floating point (ieee):	ARC-Float.

ARC little-endian output:	ARC-Opts.

ARC machine directives:	ARC-Directives.

ARC options:	ARC-Opts.

ARC support:	ARC-Dependent.

architecture options, i960:	Options-i960.

architecture options, M680x0:	M68K-Opts.

architectures, ARC:	ARC-Opts.

architectures, SPARC:	Sparc-Opts.

arguments for addition:	Infix Ops.

arguments for subtraction:	Infix Ops.

arguments in expressions:	Arguments.

arithmetic functions:	Operators.

arithmetic operands:	Arguments.

ARM floating point (ieee):	ARM Floating Point.

ARM identifiers:	ARM-Chars.

ARM line comment character:	ARM-Chars.

ARM machine directives:	ARM Directives.

ARM opcodes:	ARM Opcodes.

ARM options (none):	ARM Options.

ARM register names:	ARM-Regs.

ARM support:	ARM-Dependent.

assembler bugs, reporting:	Bug Reporting.

assembler crash:	Bug Criteria.

assembler internal logic error:	As Sections.

assembler version:	v.

assembler, and linker:	Secs Background.

assembly listings, enabling:	a.

assigning values to symbols <1>:	Equ.

assigning values to symbols:	Setting Symbols.

attributes, symbol:	Symbol Attributes.

auxiliary attributes, COFF symbols:	COFF Symbols.

auxiliary symbol information, COFF:	Dim.

Av7:	Sparc-Opts.

backslash (\\):	Strings.

backspace (\b):	Strings.

big endian output, ARC:	Overview.

big endian output, MIPS:	Overview.

big-endian output, ARC:	ARC-Opts.

big-endian output, MIPS:	MIPS Opts.

bignums:	Bignums.

binary integers:	Integers.

bitfields, not supported on VAX:	VAX-no.

block:	Z8000 Directives.

branch improvement, M680x0:	M68K-Branch.

branch improvement, VAX:	VAX-branch.

branch recording, i960:	Options-i960.

branch statistics table, i960:	Options-i960.

bss section <1>:	bss.

bss section:	Ld Sections.

bug criteria:	Bug Criteria.

bug reports:	Bug Reporting.

bugs in assembler:	Reporting Bugs.

bus lock prefixes, i386:	i386-prefixes.

bval:	Z8000 Directives.

call instructions, i386:	i386-Opcodes.

carriage return (\r):	Strings.

character constants:	Characters.

character escape codes:	Strings.

character, single:	Chars.

characters used in symbols:	Symbol Intro.

COFF auxiliary symbol information:	Dim.

COFF structure debugging:	Tag.

COFF symbol attributes:	COFF Symbols.

COFF symbol descriptor:	Desc.

COFF symbol storage class:	Scl.

COFF symbol type:	Type.

COFF symbols, debugging:	Def.

COFF value attribute:	Val.

COMDAT:	Linkonce.

command line conventions:	Command Line.

command line options, V850:	V850 Options.

command-line options ignored, VAX:	VAX-Opts.

comments:	Comments.

comments, M680x0:	M68K-Chars.

comments, removed by preprocessor:	Preprocessing.

common sections:	Linkonce.

common variable storage:	bss.

compare and jump expansions, i960:	Compare-and-branch-i960.

compare/branch instructions, i960:	Compare-and-branch-i960.

conditional assembly:	If.

constant, single character:	Chars.

constants:	Constants.

constants, bignum:	Bignums.

constants, character:	Characters.

constants, converted by preprocessor:	Preprocessing.

constants, floating point:	Flonums.

constants, integer:	Integers.

constants, number:	Numbers.

constants, string:	Strings.

continuing statements:	Statements.

conversion instructions, i386:	i386-Opcodes.

coprocessor wait, i386:	i386-prefixes.

crash of assembler:	Bug Criteria.

current address:	Dot.

current address, advancing:	Org.

D10V @word modifier:	D10V-Word.

D10V addressing modes:	D10V-Addressing.

D10V floating point:	D10V-Float.

D10V line comment character:	D10V-Chars.

D10V opcode summary:	D10V-Opcodes.

D10V optimization:	Overview.

D10V options:	D10V-Opts.

D10V registers:	D10V-Regs.

D10V size modifiers:	D10V-Size.

D10V sub-instruction ordering:	D10V-Chars.

D10V sub-instructions:	D10V-Subs.

D10V support:	D10V-Dependent.

D10V syntax:	D10V-Syntax.

data alignment on SPARC:	Sparc-Aligned-Data.

data and text sections, joining:	R.

data section:	Ld Sections.

debuggers, and symbol order:	Symbols.

debugging COFF symbols:	Def.

decimal integers:	Integers.

dependency tracking:	MD.

deprecated directives:	Deprecated.

descriptor, of a.out symbol:	Symbol Desc.

difference tables altered:	Word.

difference tables, warning:	K.

directives and instructions:	Statements.

directives, M680x0:	M68K-Directives.

directives, machine independent:	Pseudo Ops.

directives, Z8000:	Z8000 Directives.

displacement sizing character, VAX:	VAX-operands.

dot (symbol):	Dot.

doublequote (\"):	Strings.

ECOFF sections:	MIPS Object.

eight-byte integer:	Quad.

empty expressions:	Empty Exprs.

emulation:	Overview.

endianness, ARC:	Overview.

endianness, MIPS:	Overview.

EOF, newline must precede:	Statements.

error messsages:	Errors.

error on valid input:	Bug Criteria.

errors, continuing after:	Z.

escape codes, character:	Strings.

even:	Z8000 Directives.

expr (internal section):	As Sections.

expression arguments:	Arguments.

expressions:	Expressions.

expressions, empty:	Empty Exprs.

expressions, integer:	Integer Exprs.

faster processing (-f):	f.

fatal signal:	Bug Criteria.

file name, logical <1>:	File.

file name, logical:	App-File.

files, including:	Include.

files, input:	Input Files.

filling memory <1>:	Space.

filling memory:	Skip.

floating point numbers:	Flonums.

floating point numbers (double):	Double.

floating point numbers (single) <1>:	Single.

floating point numbers (single):	Float.

floating point, AMD 29K (ieee):	AMD29K Floating Point.

floating point, ARC (ieee):	ARC-Float.

floating point, ARM (ieee):	ARM Floating Point.

floating point, D10V:	D10V-Float.

floating point, H8/300 (ieee):	H8/300 Floating Point.

floating point, H8/500 (ieee):	H8/500 Floating Point.

floating point, HPPA (ieee):	HPPA Floating Point.

floating point, i386:	i386-Float.

floating point, i960 (ieee):	Floating Point-i960.

floating point, M680x0:	M68K-Float.

floating point, SH (ieee):	SH Floating Point.

floating point, SPARC (ieee):	Sparc-Float.

floating point, V850 (ieee):	V850 Floating Point.

floating point, VAX:	VAX-float.

flonums:	Flonums.

format of error messages:	Errors.

format of warning messages:	Errors.

formfeed (\f):	Strings.

functions, in expressions:	Operators.

global:	Z8000 Directives.

grouping data:	Sub-Sections.

H8/300 addressing modes:	H8/300-Addressing.

H8/300 floating point (ieee):	H8/300 Floating Point.

H8/300 line comment character:	H8/300-Chars.

H8/300 line separator:	H8/300-Chars.

H8/300 machine directives (none):	H8/300 Directives.

H8/300 opcode summary:	H8/300 Opcodes.

H8/300 options (none):	H8/300 Options.

H8/300 registers:	H8/300-Regs.

H8/300 size suffixes:	H8/300 Opcodes.

H8/300 support:	H8/300-Dependent.

H8/300H, assembling for:	H8/300 Directives.

H8/500 addressing modes:	H8/500-Addressing.

H8/500 floating point (ieee):	H8/500 Floating Point.

H8/500 line comment character:	H8/500-Chars.

H8/500 line separator:	H8/500-Chars.

H8/500 machine directives (none):	H8/500 Directives.

H8/500 opcode summary:	H8/500 Opcodes.

H8/500 options (none):	H8/500 Options.

H8/500 registers:	H8/500-Regs.

H8/500 support:	H8/500-Dependent.

hex character code (\xd...):	Strings.

hexadecimal integers:	Integers.

HPPA directives not supported:	HPPA Directives.

HPPA floating point (ieee):	HPPA Floating Point.

HPPA Syntax:	HPPA Options.

HPPA-only directives:	HPPA Directives.

i386 16-bit code:	i386-16bit.

i386 mul, imul instructions:	i386-Notes.

i386 conversion instructions:	i386-Opcodes.

i386 floating point:	i386-Float.

i386 immediate operands:	i386-Syntax.

i386 jump optimization:	i386-jumps.

i386 jump, call, return:	i386-Syntax.

i386 jump/call operands:	i386-Syntax.

i386 memory references:	i386-Memory.

i386 opcode naming:	i386-Opcodes.

i386 opcode prefixes:	i386-prefixes.

i386 options (none):	i386-Options.

i386 register operands:	i386-Syntax.

i386 registers:	i386-Regs.

i386 sections:	i386-Syntax.

i386 size suffixes:	i386-Syntax.

i386 source, destination operands:	i386-Syntax.

i386 support:	i386-Dependent.

i386 syntax compatibility:	i386-Syntax.

i80306 support:	i386-Dependent.

i960 callj pseudo-opcode:	callj-i960.

i960 architecture options:	Options-i960.

i960 branch recording:	Options-i960.

i960 compare and jump expansions:	Compare-and-branch-i960.

i960 compare/branch instructions:	Compare-and-branch-i960.

i960 floating point (ieee):	Floating Point-i960.

i960 machine directives:	Directives-i960.

i960 opcodes:	Opcodes for i960.

i960 options:	Options-i960.

i960 support:	i960-Dependent.

identifiers, AMD 29K:	AMD29K-Chars.

identifiers, ARM:	ARM-Chars.

immediate character, M680x0:	M68K-Chars.

immediate character, VAX:	VAX-operands.

immediate operands, i386:	i386-Syntax.

indirect character, VAX:	VAX-operands.

infix operators:	Infix Ops.

inhibiting interrupts, i386:	i386-prefixes.

input:	Input Files.

input file linenumbers:	Input Files.

instruction set, M680x0:	M68K-opcodes.

instruction summary, D10V:	D10V-Opcodes.

instruction summary, H8/300:	H8/300 Opcodes.

instruction summary, H8/500:	H8/500 Opcodes.

instruction summary, SH:	SH Opcodes.

instruction summary, Z8000:	Z8000 Opcodes.

instructions and directives:	Statements.

integer expressions:	Integer Exprs.

integer, 16-byte:	Octa.

integer, 8-byte:	Quad.

integers:	Integers.

integers, 16-bit:	hword.

integers, 32-bit:	Int.

integers, binary:	Integers.

integers, decimal:	Integers.

integers, hexadecimal:	Integers.

integers, octal:	Integers.

integers, one byte:	Byte.

internal assembler sections:	As Sections.

invalid input:	Bug Criteria.

invocation summary:	Overview.

joining text and data sections:	R.

jump instructions, i386:	i386-Opcodes.

jump optimization, i386:	i386-jumps.

jump/call operands, i386:	i386-Syntax.

label (:):	Statements.

labels:	Labels.

ld:	Object.

length of symbols:	Symbol Intro.

line comment character:	Comments.

line comment character, AMD 29K:	AMD29K-Chars.

line comment character, ARM:	ARM-Chars.

line comment character, D10V:	D10V-Chars.

line comment character, H8/300:	H8/300-Chars.

line comment character, H8/500:	H8/500-Chars.

line comment character, M680x0:	M68K-Chars.

line comment character, SH:	SH-Chars.

line comment character, V850:	V850-Chars.

line comment character, Z8000:	Z8000-Chars.

line numbers, in input files:	Input Files.

line numbers, in warnings/errors:	Errors.

line separator character:	Statements.

line separator, H8/300:	H8/300-Chars.

line separator, H8/500:	H8/500-Chars.

line separator, SH:	SH-Chars.

line separator, Z8000:	Z8000-Chars.

lines starting with #:	Comments.

linker:	Object.

linker, and assembler:	Secs Background.

listing control, turning off:	Nolist.

listing control, turning on:	List.

listing control: new page:	Eject.

listing control: paper size:	Psize.

listing control: subtitle:	Sbttl.

listing control: title line:	Title.

listings, enabling:	a.

little endian output, ARC:	Overview.

little endian output, MIPS:	Overview.

little-endian output, ARC:	ARC-Opts.

little-endian output, MIPS:	MIPS Opts.

local common symbols:	Lcomm.

local labels, retaining in output:	L.

local symbol names:	Symbol Names.

location counter:	Dot.

location counter, advancing:	Org.

logical file name <1>:	File.

logical file name:	App-File.

logical line number:	Line.

logical line numbers:	Comments.

lval:	Z8000 Directives.

M32R options:	M32R-Opts.

M32R support:	M32R-Dependent.

M680x0 addressing modes:	M68K-Syntax.

M680x0 architecture options:	M68K-Opts.

M680x0 branch improvement:	M68K-Branch.

M680x0 directives:	M68K-Directives.

M680x0 floating point:	M68K-Float.

M680x0 immediate character:	M68K-Chars.

M680x0 line comment character:	M68K-Chars.

M680x0 opcodes:	M68K-opcodes.

M680x0 options:	M68K-Opts.

M680x0 pseudo-opcodes:	M68K-Branch.

M680x0 size modifiers:	M68K-Syntax.

M680x0 support:	M68K-Dependent.

M680x0 syntax:	M68K-Syntax.

machine dependencies:	Machine Dependencies.

machine directives, AMD 29K:	AMD29K Directives.

machine directives, ARC:	ARC-Directives.

machine directives, ARM:	ARM Directives.

machine directives, H8/300 (none):	H8/300 Directives.

machine directives, H8/500 (none):	H8/500 Directives.

machine directives, i960:	Directives-i960.

machine directives, SH:	SH Directives.

machine directives, SPARC:	Sparc-Directives.

machine directives, V850:	V850 Directives.

machine directives, VAX:	VAX-directives.

machine independent directives:	Pseudo Ops.

machine instructions (not covered):	Manual.

machine-independent syntax:	Syntax.

macros:	Macro.

Macros, AMD 29K:	AMD29K-Macros.

macros, count executed:	Macro.

make rules:	MD.

manual, structure and purpose:	Manual.

memory references, i386:	i386-Memory.

merging text and data sections:	R.

messages from assembler:	Errors.

minus, permitted arguments:	Infix Ops.

MIPS architecture options:	MIPS Opts.

MIPS big-endian output:	MIPS Opts.

MIPS debugging directives:	MIPS Stabs.

MIPS ECOFF sections:	MIPS Object.

MIPS endianness:	Overview.

MIPS ISA:	Overview.

MIPS ISA override:	MIPS ISA.

MIPS little-endian output:	MIPS Opts.

MIPS option stack:	MIPS option stack.

MIPS processor:	MIPS-Dependent.

mnemonics for opcodes, VAX:	VAX-opcodes.

mnemonics, D10V:	D10V-Opcodes.

mnemonics, H8/300:	H8/300 Opcodes.

mnemonics, H8/500:	H8/500 Opcodes.

mnemonics, SH:	SH Opcodes.

mnemonics, Z8000:	Z8000 Opcodes.

Motorola syntax for the 680x0:	M68K-Moto-Syntax.

MRI compatibility mode:	M.

MRI mode, temporarily:	MRI.

multi-line statements:	Statements.

name:	Z8000 Directives.

named section:	Section.

named sections:	Ld Sections.

names, symbol:	Symbol Names.

naming object file:	o.

new page, in listings:	Eject.

newline (\n):	Strings.

newline, required at file end:	Statements.

null-terminated strings:	Asciz.

number constants:	Numbers.

number of macros executed:	Macro.

numbered subsections:	Sub-Sections.

numbers, 16-bit:	hword.

numeric values:	Expressions.

object file:	Object.

object file format:	Object Formats.

object file name:	o.

object file, after errors:	Z.

obsolescent directives:	Deprecated.

octal character code (\ddd):	Strings.

octal integers:	Integers.

opcode mnemonics, VAX:	VAX-opcodes.

opcode naming, i386:	i386-Opcodes.

opcode prefixes, i386:	i386-prefixes.

opcode suffixes, i386:	i386-Syntax.

opcode summary, D10V:	D10V-Opcodes.

opcode summary, H8/300:	H8/300 Opcodes.

opcode summary, H8/500:	H8/500 Opcodes.

opcode summary, SH:	SH Opcodes.

opcode summary, Z8000:	Z8000 Opcodes.

opcodes for AMD 29K:	AMD29K Opcodes.

opcodes for ARM:	ARM Opcodes.

opcodes for V850:	V850 Opcodes.

opcodes, i960:	Opcodes for i960.

opcodes, M680x0:	M68K-opcodes.

operand delimiters, i386:	i386-Syntax.

operand notation, VAX:	VAX-operands.

operands in expressions:	Arguments.

operator precedence:	Infix Ops.

operators, in expressions:	Operators.

operators, permitted arguments:	Infix Ops.

optimization, D10V:	Overview.

option summary:	Overview.

options for AMD29K (none):	AMD29K Options.

options for ARC:	ARC-Opts.

options for ARM (none):	ARM Options.

options for i386 (none):	i386-Options.

options for SPARC:	Sparc-Opts.

options for V850 (none):	V850 Options.

options for VAX/VMS:	VAX-Opts.

options, all versions of assembler:	Invoking.

options, command line:	Command Line.

options, D10V:	D10V-Opts.

options, H8/300 (none):	H8/300 Options.

options, H8/500 (none):	H8/500 Options.

options, i960:	Options-i960.

options, M32R:	M32R-Opts.

options, M680x0:	M68K-Opts.

options, SH (none):	SH Options.

options, Z8000:	Z8000 Options.

other attribute, of a.out symbol:	Symbol Other.

output file:	Object.

padding the location counter:	Align.

padding the location counter given a power of two:	P2align.

padding the location counter given number of bytes:	Balign.

page, in listings:	Eject.

paper size, for listings:	Psize.

paths for .include:	I.

patterns, writing in memory:	Fill.

plus, permitted arguments:	Infix Ops.

precedence of operators:	Infix Ops.

precision, floating point:	Flonums.

prefix operators:	Prefix Ops.

prefixes, i386:	i386-prefixes.

preprocessing:	Preprocessing.

preprocessing, turning on and off:	Preprocessing.

primary attributes, COFF symbols:	COFF Symbols.

protected registers, AMD 29K:	AMD29K-Regs.

pseudo-opcodes, M680x0:	M68K-Branch.

pseudo-ops for branch, VAX:	VAX-branch.

pseudo-ops, machine independent:	Pseudo Ops.

purpose of gnu assembler:	GNU Assembler.

real-mode code, i386:	i386-16bit.

register names, AMD 29K:	AMD29K-Regs.

register names, ARM:	ARM-Regs.

register names, H8/300:	H8/300-Regs.

register names, V850:	V850-Regs.

register names, VAX:	VAX-operands.

register operands, i386:	i386-Syntax.

registers, D10V:	D10V-Regs.

registers, H8/500:	H8/500-Regs.

registers, i386:	i386-Regs.

registers, SH:	SH-Regs.

registers, Z8000:	Z8000-Regs.

relocation:	Sections.

relocation example:	Ld Sections.

repeat prefixes, i386:	i386-prefixes.

reporting bugs in assembler:	Reporting Bugs.

return instructions, i386:	i386-Syntax.

rsect:	Z8000 Directives.

search path for .include:	I.

section override prefixes, i386:	i386-prefixes.

section-relative addressing:	Secs Background.

sections:	Sections.

sections in messages, internal:	As Sections.

sections, i386:	i386-Syntax.

sections, named:	Ld Sections.

segm:	Z8000 Directives.

SH addressing modes:	SH-Addressing.

SH floating point (ieee):	SH Floating Point.

SH line comment character:	SH-Chars.

SH line separator:	SH-Chars.

SH machine directives:	SH Directives.

SH opcode summary:	SH Opcodes.

SH options (none):	SH Options.

SH registers:	SH-Regs.

SH support:	SH-Dependent.

single character constant:	Chars.

sixteen bit integers:	hword.

sixteen byte integer:	Octa.

size modifiers, D10V:	D10V-Size.

size modifiers, M680x0:	M68K-Syntax.

size prefixes, i386:	i386-prefixes.

size suffixes, H8/300:	H8/300 Opcodes.

sizes operands, i386:	i386-Syntax.

small objects, MIPS ECOFF:	MIPS Object.

SOM symbol attributes:	SOM Symbols.

source program:	Input Files.

source, destination operands; i386:	i386-Syntax.

space used, maximum for assembly:	statistics.

SPARC architectures:	Sparc-Opts.

SPARC data alignment:	Sparc-Aligned-Data.

SPARC floating point (ieee):	Sparc-Float.

SPARC machine directives:	Sparc-Directives.

SPARC options:	Sparc-Opts.

SPARC support:	Sparc-Dependent.

special characters, M680x0:	M68K-Chars.

special purpose registers, AMD 29K:	AMD29K-Regs.

standard assembler sections:	Secs Background.

standard input, as input file:	Command Line.

statement on multiple lines:	Statements.

statement separator character:	Statements.

statement separator, H8/300:	H8/300-Chars.

statement separator, H8/500:	H8/500-Chars.

statement separator, SH:	SH-Chars.

statement separator, Z8000:	Z8000-Chars.

statements, structure of:	Statements.

statistics, about assembly:	statistics.

stopping the assembly:	Abort.

string constants:	Strings.

string literals:	Ascii.

string, copying to object file:	String.

structure debugging, COFF:	Tag.

sub-instruction ordering, D10V:	D10V-Chars.

sub-instructions, D10V:	D10V-Subs.

subexpressions:	Arguments.

subtitles for listings:	Sbttl.

subtraction, permitted arguments:	Infix Ops.

summary of options:	Overview.

support:	HPPA-Dependent.

supporting files, including:	Include.

suppressing warnings:	W.

sval:	Z8000 Directives.

symbol attributes:	Symbol Attributes.

symbol attributes, a.out:	a.out Symbols.

symbol attributes, COFF:	COFF Symbols.

symbol attributes, SOM:	SOM Symbols.

symbol descriptor, COFF:	Desc.

symbol names:	Symbol Names.

symbol names, $ in <1>:	SH-Chars.

symbol names, $ in <2>:	H8/500-Chars.

symbol names, $ in:	D10V-Chars.

symbol names, local:	Symbol Names.

symbol names, temporary:	Symbol Names.

symbol storage class (COFF):	Scl.

symbol type:	Symbol Type.

symbol type, COFF:	Type.

symbol value:	Symbol Value.

symbol value, setting:	Set.

symbol values, assigning:	Setting Symbols.

symbol versioning:	Symver.

symbol, common:	Comm.

symbol, making visible to linker:	Global.

symbolic debuggers, information for:	Stab.

symbols:	Symbols.

symbols with lowercase, VAX/VMS:	VAX-Opts.

symbols, assigning values to:	Equ.

symbols, local common:	Lcomm.

syntax compatibility, i386:	i386-Syntax.

syntax, D10V:	D10V-Syntax.

syntax, M680x0:	M68K-Syntax.

syntax, machine-independent:	Syntax.

tab (\t):	Strings.

temporary symbol names:	Symbol Names.

text and data sections, joining:	R.

text section:	Ld Sections.

Thumb support:	ARM-Dependent.

time, total for assembly:	statistics.

trusted compiler:	f.

turning preprocessing on and off:	Preprocessing.

type of a symbol:	Symbol Type.

undefined section:	Ld Sections.

unsegm:	Z8000 Directives.

V850 command line options:	V850 Options.

V850 floating point (ieee):	V850 Floating Point.

V850 line comment character:	V850-Chars.

V850 machine directives:	V850 Directives.

V850 opcodes:	V850 Opcodes.

V850 options (none):	V850 Options.

V850 register names:	V850-Regs.

V850 support:	V850-Dependent.

value attribute, COFF:	Val.

value of a symbol:	Symbol Value.

VAX bitfields not supported:	VAX-no.

VAX branch improvement:	VAX-branch.

VAX command-line options ignored:	VAX-Opts.

VAX displacement sizing character:	VAX-operands.

VAX floating point:	VAX-float.

VAX immediate character:	VAX-operands.

VAX indirect character:	VAX-operands.

VAX machine directives:	VAX-directives.

VAX opcode mnemonics:	VAX-opcodes.

VAX operand notation:	VAX-operands.

VAX register names:	VAX-operands.

VAX support:	Vax-Dependent.

Vax-11 C compatibility:	VAX-Opts.

VAX/VMS options:	VAX-Opts.

version of assembler:	v.

versions of symbols:	Symver.

VMS (VAX) options:	VAX-Opts.

warning for altered difference tables:	K.

warning messages:	Errors.

warnings, suppressing:	W.

whitespace:	Whitespace.

whitespace, removed by preprocessor:	Preprocessing.

wide floating point directives, VAX:	VAX-directives.

writing patterns in memory:	Fill.

wval:	Z8000 Directives.

Z800 addressing modes:	Z8000-Addressing.

Z8000 directives:	Z8000 Directives.

Z8000 line comment character:	Z8000-Chars.

Z8000 line separator:	Z8000-Chars.

Z8000 opcode summary:	Z8000 Opcodes.

Z8000 options:	Z8000 Options.

Z8000 registers:	Z8000-Regs.

Z8000 support:	Z8000-Dependent.

zero-terminated strings:	Asciz.


About Makertf

Makertf is a program that converts "Texinfo" files into "Rich Text Format" (RTF) files. It can be used to make WinHelp Files from GNU manuals and other documentation written in Texinfo.

Makertf is derived from GNU Makeinfo, which is a part of the GNU Texinfo documentation system.

Christian Schenk

cschenk@berlin.snafu.de